Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8458842
    Abstract: A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 11, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Li-Chung Liu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8458825
    Abstract: A jet assembly has internals rotatably and releaseably fit to a jet body, such as that for a spa. The internals have a barrel housing, a rotor and a barrel inlet. The internals as screwed into the jet body. A first threaded portion outside the barrel threadably engages second threaded portion inside the jet body wherein the internals have delimited rotation therein to align and misalign the barrel inlet from a body inlet on the jet body to control flow on and off respectively. The threaded portion within the jet body can be a locking ring affixed therein by fasteners or integral with the jet body. Rotation can be delimited by a projection on the barrel and a cooperating annular delimiting surface on the locking ring, such as circumferentially-spaced detents.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: June 11, 2013
    Assignee: Guangzhou Rising Dragon Electronics & Plastics Technology Co. Ltd.
    Inventors: Xue Wen Peng, John Keirstead, Kerry Harbarenko, Joe Hoover, Xue Wen Liu
  • Publication number: 20130141301
    Abstract: An antenna structure includes a circuit board and at least one antenna circuit. The circuit board includes a ground area and an antenna area. The antenna area is substantially rectangular-shaped and arranged between the ground area and the periphery of the circuit board. The antenna circuit is formed within the antenna area and includes a feeding segment, a border segment and at least one ground segment. The feeding segment is connected to the border segment and the distance from the border segment to the periphery of the circuit board ranges from 0 to 3 millimeters; a substantially 90° bent-structure is formed within the border segment. One end portion of the ground segment is connected to the ground area. Thus an antenna structure which enables the antenna circuit to be formed within the remaining space on the periphery of the circuit board is provided.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: AUDEN TECHNO CORP.
    Inventor: HSIEN-WEN LIU
  • Patent number: 8455319
    Abstract: A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: June 4, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung Han Lee, Chung-Yuan Lee, Hsien-Wen Liu
  • Patent number: 8450126
    Abstract: A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Yu-Wen Liu, Hao-Yi Tsai, Shin-Puu Jeng
  • Publication number: 20130122689
    Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
  • Publication number: 20130113072
    Abstract: A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20130113047
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20130113073
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20130113041
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen LIU, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8431933
    Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 30, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Hsien-Wen Liu
  • Publication number: 20130102123
    Abstract: A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 25, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tzu-Ching Tsai, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130099309
    Abstract: A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Jeng-Hsing Jang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20130093026
    Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen WANN, Ling-Yen YEH, Chi-Yuan SHIH, Yi-Tang LIN, Chih-Sheng CHANG, Chi-Wen LIU
  • Publication number: 20130096434
    Abstract: In general, the invention provides methods for use in the acquisition and display of ultrasound images. In particular, the invention provides methods for displaying ultrasound images using gating of ultrasound acquisition based on subject respiration and/or triggering ultrasound acquisition based on subject ECG. The methods may be employed with any suitable ultrasound system.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 18, 2013
    Inventors: James Mehi, Christopher A. White, Kai Wen Liu, Jerrold Wen, Desmond Hirson, Andrew Needles
  • Publication number: 20130092984
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 8420541
    Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Shing-Yih Shih, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8420545
    Abstract: The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (Toff).
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: April 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Chang Ming Wu, Yi Nan Chen, Hsien Wen Liu
  • Patent number: 8420477
    Abstract: A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 16, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo Hui Su, Yi Nan Chen, Hsien Wen Liu
  • Publication number: 20130087951
    Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Hsien-Wen Liu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu