Patents by Inventor Wen LONG

Wen LONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791227
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
  • Patent number: 11750369
    Abstract: A single round advanced encryption standard circuit module includes a substitution byte/inverse substitution byte unit, configured to substitute elements of an input state array to generate an output state array and to respectively generate a first state array, a plurality of second state arrays, a third state array, a plurality of fourth state arrays and the output state array according to a first tier circuit unit, a second tier circuit unit, a third tier circuit unit, a fourth tier circuit unit and a fifth tier circuit unit; wherein the first state array, the plurality of second state arrays, the third state array and the plurality of fourth state arrays are represented by register-transfer level codes; wherein the substitution byte/inverse substitution byte unit is implemented by composite field arithmetic of sharing operators and operands.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: September 5, 2023
    Assignee: Wistron NeWeb Corporation
    Inventors: You-Tun Teng, Wen-Long Chin
  • Patent number: 11721645
    Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11721652
    Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11699682
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11694984
    Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 4, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20230190065
    Abstract: A cleaning robot includes a main body and a cleaning module. The main body is configured to move on a floor along a travelling direction. The cleaning module includes a first shaft and some first roller sets. The first shaft is connected with the main body. The first shaft extends along a first axis perpendicular to the travelling direction. The first roller sets are separated from each other. Each first roller set includes a first bearing, a first tire and a first flexible structure. The first shaft penetrates through the first bearing. The first tire includes a first cleaning surface configured to abut against the floor. The first flexible structure includes a first inner surface and a first outer surface. The first inner surface abuts against the first bearing. The first outer surface abuts against the first tire. The first flexible structure has a first elasticity.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 22, 2023
    Inventors: Kun-Chu Wang, Wen-Long Shu, Chung-Hang Sit, Chun-Kuan Wu, Yu-Chung Hsu, Yu-Cheng Wang, Yu-Cheng Ou, Jiun-Ying Yu, Bing-Hung Yang, Hung-Ta Chiu, Chun-Chang Hung, Shih-Jung Hsu
  • Publication number: 20230190066
    Abstract: A cleaning equipment includes a first take-up reel, a first supply reel, a frame, a first cleaning film, and a transmission assembly. The frame includes an inner space accommodating the first take-up reel and the first supply reel side by side and an outer surface having at least one gap communicating with the inner space. The first cleaning film has a supply part on the first supply reel, a take-up part on the first take-up reel, and a middle part at least partially covering the outer surface of the frame. Two ends of the middle part enter the inner space through the at least one gap and are connected to the supply part and the take-up part, respectively. The transmission assembly is coupled to the first supply reel and the first take-up reel and drives at least one of the first supply reel and the first take-up reel to rotate.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 22, 2023
    Inventors: CHUNG HANG SIT, WEN LONG SHU, CHUN KUAN WU, YU-CHUNG HSU, KUN-CHU WANG, YU CHENG OU, JIUN-YING YU, BING HUNG YANG, HUNG-TA CHIU, YU-CHENG WANG
  • Patent number: 11670513
    Abstract: Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.
    Type: Grant
    Filed: April 11, 2021
    Date of Patent: June 6, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yueh Sheng Ow, Junqi Wei, Wen Long Favier Shoo, Ananthkrishna Jupudi, Takashi Shimizu, Kelvin Boh, Tuck Foong Koh
  • Publication number: 20230027674
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
  • Publication number: 20220415739
    Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Patent number: 11538760
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a lower conductive structure, a first semiconductor device and a second semiconductor device. The upper conductive structure is disposed on the lower conductive structure. The second semiconductor device is electrically connected to the first semiconductor device by a first path in the upper conductive structure. The lower conductive structure is electrically connected to the first semiconductor device through a second path in the upper conductive structure under the first path.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: December 27, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11532542
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and a plurality of conductive through vias. The conductive structure includes a dielectric layer, a circuit layer in contact with the dielectric layer, a plurality of dam portions and an outer metal layer. The dam portions extend through the dielectric layer. The dam portion defines a through hole. The outer metal layer is disposed adjacent to a top surface of the dielectric layer and extends into the through hole of the dam portion. The conductive through vias are disposed in the through holes of the dam portions and electrically connecting the circuit layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 20, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11505457
    Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: November 22, 2022
    Assignee: XINTEC INC.
    Inventors: Yu-Tang Shen, Shun-Wen Long, Chih-Hung Cho, Hsing-Yuan Chu
  • Publication number: 20220367304
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuoching CHENG, Yuan-Feng CHIANG, Ya Fang CHAN, Wen-Long LU, Shih-Yu WANG
  • Patent number: 11495557
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jhao-Cheng Chen, Huang-Hsien Chang, Wen-Long Lu, Shao Hsuan Chuang, Ching-Ju Chen, Tse-Chuan Chou
  • Publication number: 20220337395
    Abstract: A single round advanced encryption standard circuit module includes a substitution byte/inverse substitution byte unit, configured to substitute elements of an input state array to generate an output state array and to respectively generate a first state array, a plurality of second state arrays, a third state array, a plurality of fourth state arrays and the output state array according to a first tier circuit unit, a second tier circuit unit, a third tier circuit unit, a fourth tier circuit unit and a fifth tier circuit unit; wherein the first state array, the plurality of second state arrays, the third state array and the plurality of fourth state arrays are represented by register-transfer level codes; wherein the substitution byte/inverse substitution byte unit is implemented by composite field arithmetic of sharing operators and operands.
    Type: Application
    Filed: August 17, 2021
    Publication date: October 20, 2022
    Applicant: Wistron NeWeb Corporation
    Inventors: You-Tun Teng, Wen-Long Chin
  • Publication number: 20220332571
    Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 20, 2022
    Inventors: Yu-Tang SHEN, Shun-Wen LONG, Chih-Hung CHO, Hsing-Yuan CHU
  • Publication number: 20220301620
    Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a plurality of sensing operations respectively corresponding to a plurality of sensing voltages to generate a first digital value and a second digital value of the Flash cell, the second digital value representing at least one candidate threshold voltage of the Flash cell; determining a threshold voltage of the Flash cell according to whether the at least one candidate threshold voltage is high or low; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
    Type: Application
    Filed: June 5, 2022
    Publication date: September 22, 2022
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
  • Patent number: 11430708
    Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu