Abstract: A dielectric composition and an electronic component containing the dielectric composition. A concentration of a first rare earth element at a center of a specific main phase grain having a grain size equal to or larger than an average grain size (D50) of main phase grains observed in a cross section is defined as RA1, a concentration of the first rare earth element at a center of a triple point segregation is defined as RA2, a concentration of a second rare earth element at the center of the specific main phase grain is defined as RB1, a concentration of the second rare earth element at the center of the triple point segregation is defined as RB2, RA2/RA1 is 1.0 or more and 2.5 or less, and RB2/RB1 is 3.0 or more and 9.0 or less (preferably 5.0 or more and 7.0 or less).

Abstract: A laser soldering method using dynamic light spot is provided and includes following steps: executing a soldering to control a laser module to radiate toward multi-lens to form a light spot on a soldering target; and, adjusting a lens distance between the multi-lens based on a spot-adjustment condition to adjust a light spot size of the light spot when the spot-adjustment condition is met in the soldering. The disclosure may provide multiple heating densities respectively adequate to different soldering status via adjusting the light spot size when using same laser power, so as to improve the soldering quality.

Abstract: A chip for testing an impedance of a battery module, can include: at least one current excitation port configured to control an excitation current applied to the battery module; at least one voltage sampling port configured to sample a response voltage generated on the battery module; a control module configured to perform Fourier transform on the excitation current and the response voltage to generate impedance information of the battery module; and where the excitation current is configured as a superposition signal of at least two square wave current signals with different frequencies.

Abstract: A heat dissipation module includes a plurality of thermally conductive components and a first heat dissipation fin assembly. Each of the thermally conductive components includes a heat absorption portion and a first condensation portion. The first condensation portion includes a first connection portion and a first bent portion, and two ends of the first connection portion are respectively connected to the first bent portion and the heat absorption portion. The first heat dissipation fin assembly is connected to the first bent portion of the first condensation portion of each of the thermally conductive components.

Abstract: A semiconductor cell structure includes a semiconductor substrate with an original semiconductor surface having a first set active regions and a second set of active regions; a STI region surrounding the first set and the second set active regions, a set of PMOS transistors disposed in the first set active regions; a set of NMOS transistors disposed in the second set of active regions; a VDD contacting line electrically coupled to the set of PMOS transistors; a VSS contacting line electrically coupled to the set of NMOS transistors; wherein a bottom surface of each of the source regions and drain regions of the PMOS transistors and the NMOS transistors is isolated from the semiconductor substrate by a localized insulator region, and these localized insulator regions are disposed below the original semiconductor surface.

Abstract: The disclosed technology is directed towards switching the primary cell in a carrier aggregation scenario to improve performance. Measurement data of a mobile device (user equipment) is evaluated with respect to one or more various criteria such as cell carrier bandwidth, cell carrier load, cell-related capability and other carrier data (e.g., dynamic spectrum sharing versus clean, time division duplex or frequency division duplex), and others. Device conditions such as overheating can be considered as well. The evaluation results in a ranking of primary cell candidates. If a more optimal primary cell (candidate) is available, the primary cell in the carrier aggregation combination is switched to the candidate that is ranked the highest. Switching can be relatively very fast, such as based on already existing layer-1 (L1) and/or layer-2 (L2) measurement data. Layer-3 (L3) measurement data also can be obtained on demand, for example, to use in the evaluation.

Abstract: A video decoding method includes: receiving an encoded video bitstream, and decoding a first block. The encoded video bitstream includes data to be decoded as the first block of pixels in a picture, and the first block includes a luma block and at least one chroma block. Decoding the first block includes: determining whether to apply a neural network (NN) filter on the luma block and the at least one chroma block according to an NN filter mode of the luma block and at least one NN filter mode of the at least one chroma block.

Abstract: A multi-layer detachable single-axis fiber optic sensing device is provided. The device includes a first circuit board, a light source module, an optical carrier, a beam guiding module, a modulation module, a fiber coil, a second circuit board, a detection module, a third circuit board, a transceiver module, a fourth circuit board, a power supply module, a fifth circuit board, and a computing module. The first circuit board, the optical carrier, the second circuit board, the third circuit board, the fourth circuit board, and the fifth circuit board may be arranged in any order, and any two adjacent ones can be detachably assembled together.

Abstract: Immersion thermal management systems are provided for managing thermal energy in a traction battery pack. An exemplary immersion thermal management system may utilize an edge cooling scheme in which a coolant contacts minor side surfaces (e.g., top, bottom, and ends) of battery cells of the traction battery pack but does not flow across major side surfaces (e.g., faces) of the battery cells. The edge cooling scheme provides adequate cooling without adding volume and mass to the traction battery pack.

Abstract: A control circuit for a switching converter includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal and a reference signal. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal to the switching converter. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.

Abstract: A driver circuit including a switch circuit and a source driver circuit is provided. The switch circuit is configured to receive an input display data and output an output display data according to two control signals. The input display data and the output display data have different data arrangement. The source driver circuit is coupled to the switch circuit. The source driver circuit is configured to output the output display data to drive a display panel via the switch circuit. An applying sequence of the two control signals is adjusted according to at least one adjustment signal, and the two control signals are applied to switch sets of the switch circuit according to the applying sequence.

Abstract: A method includes providing a semiconductor substrate, and forming first and second metal gate stacks in a dummy region of the semiconductor substrate and third metal gate stacks in an active device region of the semiconductor substrate. The active device region is surrounded by the dummy region and includes a main area and a tip area protruding from the main area in a top view. The first metal gate stacks are associated with the tip area and having a first pattern density, and the second metal gate stacks are associated with the main area and having a second pattern density greater than the first pattern density. The method further includes performing a chemical mechanical polishing (CMP) process to the first, the second, and the third metal gate stacks. After the CMP process, the third metal gate stacks in the tip area and in the main area have a same height.

Abstract: A method for forming a patterned mask layer is provided. The method includes forming a layer over a substrate and forming a first strip structure and a second strip structure over the layer. The method also includes forming a spacer layer between the first strip structure, the second strip structure, and the layer. The spacer layer has an H-shape, the spacer layer has a first trench and a second trench spaced apart from each other, and the first trench and the second trench expose portions of the layer. The method further includes forming a third strip structure and a fourth strip structure in the first trench and the second trench, respectively. In addition, the method includes removing the spacer layer. The first strip structure, the second strip structure, the third strip structure, and the fourth strip structure together form a patterned mask layer.

Abstract: A semiconductor processing apparatus and a method, comprising: positioning a second chamber at an open position relative to a first chamber; positioning a semiconductor wafer to be processed between the first chamber and the second chamber; positioning the second chamber at a closed position relative to the first chamber; introducing an etching mixed gas into a sealed channel, wherein the etching mixed gas etches a partial surface of the semiconductor wafer, followed by discharging exhaust gas from the sealed channel; introducing a predetermined amount of extraction liquid into the sealed channel, wherein the extraction liquid is driven to flow through the sealed channel until exiting the sealed channel to extract metal contaminants. This method significantly reduces chemical consumption while improving etching depth precision, extraction solution control, etching uniformity, and surface roughness.

Abstract: Aspects of the present disclosure are directed to quantitatively tracking food intake using smart glasses and/or other wearable devices. In some implementations, the smart glasses can include an image capture device, such as a camera, that can seamlessly capture images of food being eaten by the user. A computing device in communication with the smart glasses (or the smart glasses themselves) can identify the type and volume of food being eaten by applying object recognition and volume estimation techniques to the images. Additionally or alternatively, the smart glasses and/or other wearable devices can track a user's eating patterns through the number of bites taken throughout the day by capturing and analyzing hand-to-mouth motions and chewing. The computing device can log the type of food, volume of food, and/or number of bites taken and compute statistics that can be displayed to the user on the smart glasses.

Abstract: Methods and apparatus for scheduling uplink transmissions based on contributiveness to a downstream task are provided. Multiple devices to schedule for uplink transmission are selected from a set of candidate devices based on a contributiveness metric for each device. The contributiveness metric for each device is related to a downstream task in the wireless communication network and is indicative of how well the device is able to successfully transmit information to the network for the downstream task and how informative the information provided by the device is for the downstream task. The contributiveness metric of a candidate device may be learned via machine learning using a deep neural network.

Abstract: The present application relates to adenovirus virus-like particles (AdVLPs) and related compositions, plasmids, and methods. The AdVLP can include a recombinant capsid that comprises major capsid adenovirus (AdV) proteins such as a hexon protein, a penton protein, and a fiber protein, and minor capsid/cement AdV proteins, such as a Illa protein, a VI protein, a VIII protein, and a IX protein. The minor capsid/cement AdV proteins structurally support the major capsid AdV proteins. The recombinant capsid of the AdVLP can further include a chaperone AdV protein, and an accessory scaffold AdV protein.

Abstract: The present invention describes heat sinks (100) in which fins (120) are hybrid 3D printed using laser powder-bed fusing (LPBF) or selective laser melting (SLM) (200) of a fin powder (122) deposited directly over a substrate (140). The fin powder (122) forms a powder-bed, which height is increased, layer by layer, and the fins (120) are being built up, layer by layer, by laser melting and fusing the fin powder (122). The fin powder (122) may be copper, copper alloy, aluminium or aluminium alloy, whilst the associated substrate (140) is copper-based or aluminium-based. The substrate (140) is prepared by conventional machining, hence, the process (200) is called hybrid LPBF or SLM. The heat sinks (100) obtained have excellent heat dissipation and temperature stability performances.

Abstract: The present application discloses a device and method for preparing aromatic hydrocarbons by coupling naphtha and methanol. By adopting the device, under an action of a catalyst, the naphtha and the methanol react to generate product gas with aromatic hydrocarbons and a low-carbon olefin as main components. By the method of the application, linear-chain and branched-chain aliphatic hydrocarbons can be efficiently converted into aromatic hydrocarbons in a highly selective mode, a yield of p-xylene is also increased through a methylation reaction of aromatic hydrocarbons, and a content of p-xylene in a xylene mixture is greater than 75 wt %.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a thin film resistor (TFR) with a taper profile. The semiconductor structure further includes a first contact physically contacting a first portion of the TFR. The semiconductor structure includes a second contact physically contacting a second portion of the TFR. The semiconductor structure further includes an oxide layer, over the second dielectric layer and surrounding the first contact and the second contact, and an inter-metal dielectric (IMD) layer over the oxide layer. The IMD layer is substantially free of voids and surrounds a first metal plug physically contacting the first contact and a second metal plug physically contacting the second contact.