Patents by Inventor Wen Shen

Wen Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image Sensor
    Publication number: 20140340552
    Abstract: An image sensor includes a pixel unit and a pixel readout circuit. The pixel unit includes an image pixel array including a plurality of image pixel columns, respectively; a first reference pixel array including a plurality of first reference pixel columns; and a bias circuit, coupled to the image pixel columns for generating a plurality of column sensing signals, coupled to the first reference pixel columns for generating a plurality of first reference signals, and further for generating a first average reference voltage signal according to the plurality of first reference signals. The pixel readout circuit generates a plurality of reset values and a plurality of sampling values according to the column sensing signals and the first average reference voltage signal, wherein the plurality of reference pixel rows is less than the plurality of image pixel rows.
    Type: Application
    Filed: March 13, 2014
    Publication date: November 20, 2014
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Wen-Shen Wuen, Chao-Yu Meng
  • OXIDATION-RESISTANT AND WEAR-RESISTANT POLYETHYLENES FOR HUMAN JOINT REPLACEMENTS AND METHODS FOR MAKING THEM
    Publication number: 20140235745
    Abstract: The present invention presents methods for making oxidation-resistant and wear-resistant polyethylenes and medical implants made therefrom. Preferably, the implants are components of prosthetic joints, e.g., a bearing component of an artificial hip or knee joint. The resulting oxidation-resistant and wear-resistant polyethylenes and implants are also disclosed.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Inventors: Harry A. McKellop, Fu-Wen Shen
  • Oxidation-resistant and wear-resistant polyethylenes for human joint replacements and methods for making them
    Patent number: 8796347
    Abstract: The present invention presents methods for making oxidation-resistant and wear-resistant polyethylenes and medical implants made therefrom. Preferably, the implants are components of prosthetic joints, e.g., a bearing component of an artificial hip or knee joint. The resulting oxidation-resistant and wear-resistant polyethylenes and implants are also disclosed.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: August 5, 2014
    Assignee: Orthopaedic Hospital
    Inventors: Harry A. McKellop, Fu-Wen Shen
  • Layout of a MOS array edge with density gradient smoothing
    Patent number: 8759163
    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Jui-Cheng Huang
  • ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER
    Publication number: 20140159932
    Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Ho Chang, Yung-Chow Peng, Jui-Cheng Huang, Wen-Shen Chou
  • Graded dummy insertion
    Patent number: 8719755
    Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shen Chou, Yung-Chow Peng, Chih-Chiang Chang, Chin-Hua Wen
  • Area optimized series gate layout structure for FINFET array
    Patent number: 8719759
    Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shen Chou, Chin-Hua Wen, Yung-Chow Peng, Chih-Chiang Chang
  • Layout Schemes for Cascade MOS Transistors
    Publication number: 20140110787
    Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hua Wen, Wen-Shen Chou
  • Macro cell based process design kit for advanced applications
    Patent number: 8701055
    Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Wen-Shen Chou
  • Correlated double sampling device of image sensor and method thereof
    Patent number: 8692915
    Abstract: A correlated double sampling device (CDS device) of an image sensor is provided. The CDS device is coupled to a plurality of light-sensing pixels arranged along a first direction. The CDS device of the image sensor includes a regulator and a sampling circuit. The regulator provides the light-sensing pixels with a first voltage so that at least one of the light-sensing pixels provides a first linear current and a second linear current according to the first voltage. The sampling circuit is coupled between a second voltage and the regulator and includes a first sampling unit and a second sampling unit to respectively receive the first linear current for a first duration and the second linear current for a second duration and to respectively and correspondingly output a first sampling signal and a second sampling signal.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jer-Hao Hsu, Chao-Yu Meng, Wen-Shen Wuen
  • Oxidation-resistant and wear-resistant polyethylenes for human joint replacements and methods for making them
    Patent number: 8658710
    Abstract: The present invention presents methods for making oxidation-resistant and wear-resistant polyethylenes and medical implants made therefrom. Preferably, the implants are components of prosthetic joints, e.g., a bearing component of an artificial hip or knee joint. The resulting oxidation-resistant and wear-resistant polyethylenes and implants are also disclosed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: February 25, 2014
    Assignee: Orthopaedic Hospital
    Inventors: Harry A. McKellop, Fu-Wen Shen
  • SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM
    Publication number: 20140042585
    Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow PENG, Wen-Shen CHOU, Jaw-Juinn HORNG
  • GRADED DUMMY INSERTION
    Publication number: 20140040836
    Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shen Chou, Yung-Chow Peng, Chih-Chiang Chang, Chin-Hua Wen
  • Digital-to-analog converter
    Patent number: 8599057
    Abstract: A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Lai, Mei-Chen Chuang, Wen-Shen Chou
  • LDO regulators for integrated applications
    Patent number: 8598854
    Abstract: An amplifier drives the gate of a master source follower and of at least one slave source follower to form a low-dropout (LDO) regulator. Alternatively, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Soenen, Alan Roth, Justin Shi, Ying-Chih Hsu, Guang-Cheng Wang, Wen-Shen Chou
  • Bumper for an automobile
    Patent number: D711795
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 26, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jin Won Kim, Alexander Wen Shen, Michio Tada
  • Automobile
    Patent number: D714695
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 7, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jin Won Kim, Alexander Wen Shen, Etsuya Ohishi, Michio Tada
  • Motor vehicle and/or toy replica thereof
    Patent number: D715194
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jin Won Kim, Alexander Wen Shen, Etsuya Ohishi, Michio Tada, Ken Nagasaka
  • Automobile
    Patent number: D715200
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jin Won Kim, Alexander Wen Shen, Etsuya Ohishi, Ken Nagasaka, Michio Tada
  • Combination lamp for an automobile
    Patent number: D715471
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Ken Nagasaka, Jin Won Kim, Alexander Wen Shen, Michio Tada