Patents by Inventor Wen Shen

Wen Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10370659
    Abstract: In certain embodiments, the present disclosure provides compounds and methods for increasing the antisense activity of an antisense compound in a cell. In certain embodiments, the present disclosure provides methods for identifying antisense compounds having high activity. In certain embodiments, the present disclosure provides methods for identifying antisense compounds that bind to enhancer or repressor proteins.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 6, 2019
    Assignee: Ionis Pharmaceuticals, Inc.
    Inventors: Xue-hai Liang, Wen Shen, Stanley T. Crooke
  • Publication number: 20190230895
    Abstract: A pet combination house includes a housing and a connecting unit. The housing includes a plurality of plates, with a folding line being formed at a connection of two plates. The plates are folded upward along the folding line and are connected together to construct the housing. Some of the plates have a side respectively provided with a fastening member. The fastening members of the plates are detachably combined together in pairs when the housing is disposed at the three-dimensional state. At least one of the plates is provided with an opening. At least one of the plates has a face provided with a plurality of apertures. The connecting unit includes a plurality of retaining members mounted on the plates and aligning with the apertures, and a plurality of connecting members mounted in the apertures and retained by the retaining members.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: Chih-Hung Lin, Li- Wen Shen
  • Patent number: 10359668
    Abstract: A display device including a display panel and a backlight module is provided. The backlight module is correspondingly disposed below the display panel and includes light-emitting elements providing light beams and disposed on a circuit board, lens units each being disposed on a corresponding light-emitting element and having a concave inside surface covering the corresponding light-emitting element and a convex outside surface covering the concave inside surface, and an inverse prism sheet disposed between the lens units and the display panel, and the inverse prism sheet having inverse prisms with a vertex corner. At least a portion of the light beams emitted from the convex outside surface each has a predetermined light-emitting angle ?o larger than 30 degrees and less than 90 degrees. The backlight module has a height of cavity D being a distance between the vertex corner and the circuit board, and 10 ?m?D<30 mm.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 23, 2019
    Assignee: INNOLUX CORPORATION
    Inventor: Wen-Shen Yu
  • Publication number: 20190203165
    Abstract: A cell culture module, a cell culture system and a cell culture method are provided. The cell culture module includes a casing, a first fixer, a second fixer and a sheet-shaped carrier member. The casing has a chamber and at least one inlet/outlet. The inlet/outlet communicates with the chamber. The first fixer is fixed to the casing and located in the chamber. The second fixer is disposed in the chamber and is movable relative to the first fixer. The sheet-shaped carrier member is formed by arranging a plurality of cell culture carriers, and two opposite ends of the sheet-shaped carrier member are respectively fixed to the first fixer and the second fixer. The sheet-shaped carrier member is in an open state or a folded state according to a variation in a distance between the first fixer and the second fixer due to a movement of the second fixer.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Ing-Kae Wang, Ying-Wen Shen, Yea-Tzy Deng, Den-Tai Lin, Yu-Bing Liou, Sing-Ying Hsieh, Wei-Zhou Yeh, Meng-Hua Yang, Hsiang-Chun Hsu, Ying-Chun Chien
  • Publication number: 20190195943
    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Zeng KANG, Chih-Hsien CHANG, Wen-Shen CHOU, Yung-Chow PENG
  • Publication number: 20190179993
    Abstract: The present disclosure describes a method for replacing a device with a cell structure having a plurality of uni-gates. An exemplary method includes receiving a circuit diagram that includes the device, determining the cell structure wherein a cumulative effective gate length of the plurality of uni-gates is equal to a gate length of the device, generating, based on the cell structure and the device, a floor plan that includes an arrangement of a plurality of placeholders that match an arrangement of the cell structure and an arrangement of the device in the circuit diagram, and generating a circuit layout based on the floor plan, the cell structure, and the circuit diagram. The plurality of placeholders is replaced by the cell structure and the cell structure is connectable to other parts of the circuit diagram based on the circuit diagram.
    Type: Application
    Filed: August 14, 2018
    Publication date: June 13, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shen CHOU, Po-Zeng KANG, Yung-Chow PENG, Yung-Hsu CHUANG, Yu-Tao YANG
  • Patent number: 10281501
    Abstract: A peak current evaluation apparatus for an IC is provided. The peak current evaluation apparatus includes a pulse tuner and a testing circuit. The pulse tuner receives a clock signal, adjusts pulse width and duty ratio of the clock signal according to at least one predetermined parameter in order to generate a pulse signal with a stress voltage. The testing circuit is coupled to the pulse tuner. The testing circuit, which includes two input ports, receives the pulse signal at one of the two input ports in order to stress a testing device, measures the resistance value of the testing device, and calculates the peak current of the testing device when the resistance value increases and exceeds a threshold value.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 10274536
    Abstract: A device comprising a device under test and a time to current converter configured to be coupled to the device under test. The device under test comprises: (i) at least one delay element for creating a delay; (ii) at least one capacitor for providing capacitance loading to the at least one delay element; and (iii) at least one switch to control the capacitance loading provided by the at least one capacitor. The time to current converter comprises (i) a first input for receiving a first clock signal; (ii) a second input for receiving an inverted and delayed version of the first clock signal from the device under test; and (iii) an impedance module for measuring an output current. During a testing mode, the at least one switch is in a closed position so the at least one capacitor can provide a capacitance loading to the at least one delay element to amplify the delay associated with the device under test.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yung-Chow Peng, Po-Zeng Kang, Wen-Shen Chou, Yu-Tao Yang
  • Publication number: 20190094277
    Abstract: An integrated circuit (IC) includes a first transistor having a first dopant type and a second transistor having a second dopant type opposite to the first dopant type. The first transistor includes a first terminal configured to receive a current, a second terminal connected to a node, and a first gate, and the second transistor includes a first terminal connected to a device under test (DUT), a second terminal connected to the node, and a second gate. Each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Wen-Shen CHOU, Po-Zeng KANG, Yung-Chow PENG
  • Publication number: 20190079642
    Abstract: A system and method for controlling a computerized device's display to provide a user interface that renders compact and informative graphical user interface images, particularly in a medical care management device in which a large amount of information is required by the user, and a size of the display device is relatively small. The system and method can deliver structured guidance to medical personnel to promote rendering of medical care in compliance with predetermined care protocols, and automatedly logs, and/or guides the user to log, events and occurrences during the medical emergency for accurate logging of same. Multiple independent cyclical numerical task timers, graphical progress indicators, and cycle counters may be displayed concurrently within a single field of view/window within a display device's display area. Expiration of a cycle time may be reflected by a color change, and initiate text or other prompting according to a predefined care protocol.
    Type: Application
    Filed: August 21, 2018
    Publication date: March 14, 2019
    Inventors: Catherine Burch, Erwin V. Bautista, Michael G. Benninghoff, John Gerard DiGiovanni, Mithil Gajera, Jason A. Mastriana, Jonathan Michael Meade, Dannette Arlene Newby Mitchell, Bridget A. Remel, Nelida Rios, Wen Shen
  • Patent number: 10222412
    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Zeng Kang, Chih-Hsien Chang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20190051666
    Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 14, 2019
    Inventors: Wen-Shen Li, XIAOYUAN ZHI, XINGXING CHEN, Ching-Yang Wen
  • Patent number: 10161976
    Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Shen Chou, Po-Zeng Kang, Yung-Chow Peng
  • Patent number: 10161977
    Abstract: A circuit for measuring a gain of an amplifier includes a first node coupled to an output of the amplifier, a second node, a first circuit coupled to an input and the output of the amplifier, and a second circuit coupled between the first circuit and the second node. The first circuit is configured to cause a first gain drop in a gain to be measured between the first node and the second node. The second circuit configured to cause a second gain drop in the gain to be measured between the first node and the second node.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Brady Yang, Wen-Shen Chou
  • Patent number: 10141934
    Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20180323182
    Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 8, 2018
    Inventors: Yung-Chow PENG, Wen-Shen CHOU, Jaw-Juinn HORNG
  • Publication number: 20180321291
    Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Wen-Shen CHOU, Po-Zeng KANG, Yung-Chow PENG
  • Publication number: 20180315714
    Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a circuit board, a chip, a housing, an antenna pattern, a conductive line pattern and a shielding layer. The chip is disposed on the circuit board. The housing is disposed on the circuit board and covers the chip, wherein the housing includes a cover and sidewalls, and the housing contains catalyst particles. The antenna pattern is disposed on an outer surface of the cover. The conductive line pattern is disposed on an outer surface of the sidewalls and electrically connected to the antenna pattern and the circuit board. The shielding layer is disposed at least on an inner surface of the cover.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Jui-Chun Kuo, Chuang-Yi Chiu, Kuei-Sheng Wu, Wen-Shen Lo
  • Patent number: 10102792
    Abstract: A driving circuit of a display panel and a display apparatus using the same are provided. The driving circuit includes a shift register, a latch, a level shifter, a current source and a charge switch. The shift register receives a trigger signal to provide a data latch signal. The latch couples to the shift register, and receives a gray-level data to latch and output the gray-level data according to the data latch signal. The level shifter couples to the latch and provides a charge switch signal according to the gray-level data. The current source provides a charge current. The charge switch couples between the current source and a pixel of the display panel, and receives the charge switch signal to determine whether the current source is coupled to the pixel according to the charge switch signal.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: October 16, 2018
    Assignee: Novatek Microelectronics Corp.
    Inventors: Ying-Neng Huang, Wen-Shen Wuen
  • Publication number: 20180223238
    Abstract: A cell culture carrier module and a cell culture system having the same are provided. A cell tank and a culture medium module respectively communicate with the carrier module. The carrier module includes a reactor, a first fixer, a second fixer and a plurality of cell culture carriers. The reactor has a chamber and at least one inlet/outlet. The inlet/outlet communicates with the chamber. The first fixer is fixed to the reactor and located in the chamber. The second fixer is disposed in the chamber and is movable relative to the first fixer. Two ends of each cell culture carrier are fixed to the first fixer and the second fixer, respectively. The cell culture carriers are in an untwisted state or a twisted state according to a variation in a distance between the first fixer and the second fixer due to a movement of the second fixer.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 9, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Ying-Wen Shen, Ing-Kae Wang, Chia-Jung Lu, Yea-Tzy Deng, Yu-Bing Liou, Sing-Ying Hsieh, Hsin-Hsin Shen, Hsiu-Ying Wang