Abstract: An integrated circuit (IC) includes a first transistor having a first dopant type and a second transistor having a second dopant type opposite to the first dopant type. The first transistor includes a first terminal configured to receive a current, a second terminal connected to a node, and a first gate, and the second transistor includes a first terminal connected to a device under test (DUT), a second terminal connected to the node, and a second gate. Each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.

Abstract: A system and method for controlling a computerized device's display to provide a user interface that renders compact and informative graphical user interface images, particularly in a medical care management device in which a large amount of information is required by the user, and a size of the display device is relatively small. The system and method can deliver structured guidance to medical personnel to promote rendering of medical care in compliance with predetermined care protocols, and automatedly logs, and/or guides the user to log, events and occurrences during the medical emergency for accurate logging of same. Multiple independent cyclical numerical task timers, graphical progress indicators, and cycle counters may be displayed concurrently within a single field of view/window within a display device's display area. Expiration of a cycle time may be reflected by a color change, and initiate text or other prompting according to a predefined care protocol.

Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.

Abstract: A circuit for measuring a gain of an amplifier includes a first node coupled to an output of the amplifier, a second node, a first circuit coupled to an input and the output of the amplifier, and a second circuit coupled between the first circuit and the second node. The first circuit is configured to cause a first gain drop in a gain to be measured between the first node and the second node. The second circuit configured to cause a second gain drop in the gain to be measured between the first node and the second node.

Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.

Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.

Abstract: A method of measuring an output resistance of a DUT includes determining an initial output resistance of an n-type transistor, thereby determining an initial gate voltage for the n-type transistor, and determining an initial output resistance of a p-type transistor, thereby determining an initial gate voltage for the n-type transistor. A resistance for a cascode arrangement of the n-type transistor and the p-type transistor is determined, and the output resistance of the DUT using the cascode arrangement is measured by biasing the n-type transistor with the initial gate voltage for the n-type transistor and biasing the p-type transistor with the initial gate voltage for the p-type transistor.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a circuit board, a chip, a housing, an antenna pattern, a conductive line pattern and a shielding layer. The chip is disposed on the circuit board. The housing is disposed on the circuit board and covers the chip, wherein the housing includes a cover and sidewalls, and the housing contains catalyst particles. The antenna pattern is disposed on an outer surface of the cover. The conductive line pattern is disposed on an outer surface of the sidewalls and electrically connected to the antenna pattern and the circuit board. The shielding layer is disposed at least on an inner surface of the cover.

Abstract: A driving circuit of a display panel and a display apparatus using the same are provided. The driving circuit includes a shift register, a latch, a level shifter, a current source and a charge switch. The shift register receives a trigger signal to provide a data latch signal. The latch couples to the shift register, and receives a gray-level data to latch and output the gray-level data according to the data latch signal. The level shifter couples to the latch and provides a charge switch signal according to the gray-level data. The current source provides a charge current. The charge switch couples between the current source and a pixel of the display panel, and receives the charge switch signal to determine whether the current source is coupled to the pixel according to the charge switch signal.

Abstract: A cell culture carrier module and a cell culture system having the same are provided. A cell tank and a culture medium module respectively communicate with the carrier module. The carrier module includes a reactor, a first fixer, a second fixer and a plurality of cell culture carriers. The reactor has a chamber and at least one inlet/outlet. The inlet/outlet communicates with the chamber. The first fixer is fixed to the reactor and located in the chamber. The second fixer is disposed in the chamber and is movable relative to the first fixer. Two ends of each cell culture carrier are fixed to the first fixer and the second fixer, respectively. The cell culture carriers are in an untwisted state or a twisted state according to a variation in a distance between the first fixer and the second fixer due to a movement of the second fixer.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A testing structure includes a first transistor having a first dopant type connected to a current source. The testing structure further includes a second transistor having a second dopant type, opposite to the first dopant type. The second transistor is connected to a device under test (DUT). The second transistor is connected in series with the first transistor in a cascode arrangement. The cascode arrangement is capable of measuring an output resistance of the DUT of greater than 1 mega-ohm (M?).

Abstract: A peak current evaluation apparatus for an IC is provided. The peak current evaluation apparatus includes a pulse tuner and a testing circuit. The pulse tuner receives a clock signal, adjusts pulse width and duty ratio of the clock signal according to at least one predetermined parameter in order to generate a pulse signal with a stress voltage. The testing circuit is coupled to the pulse tuner. The testing circuit, which includes two input ports, receives the pulse signal at one of the two input ports in order to stress a testing device, measures the resistance value of the testing device, and calculates the peak current of the testing device when the resistance value increases and exceeds a threshold value.

Abstract: A circuit for measuring a bandwidth of an amplifier includes first and second capacitors, first through third switches, and a pulse generator. First terminals of the capacitors are coupled to an amplifier input, and a second terminal of the second capacitor is coupled to an amplifier output. The first switch has a control terminal and terminals coupled to a first input node and a second terminal of the first capacitor. The second switch has a control terminal and terminals coupled to the amplifier input and output. The third switch has a control terminal, a first terminal, and a second terminal coupled to the second terminal of the first capacitor. The pulse generator has a first output coupled to the control terminal of the third switch, and is configured to vary a pulse width of a pulse signal supplied from the first output to the control terminal of the third switch.

Abstract: In certain embodiments, the present disclosure provides compounds and methods for increasing the antisense activity of an antisense compound in a cell. In certain embodiments, the present disclosure provides methods for identifying antisense compounds having high activity. In certain embodiments, the present disclosure provides methods for identifying antisense compounds that bind to enhancer or repressor proteins.

Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.

Abstract: A circuit for measuring a bandwidth of an amplifier includes a switch-capacitor circuit and a controller. The switch-capacitor circuit is coupled to an output and an input of the amplifier. The switch-capacitor circuit is switchable between a sampling mode and an amplification mode. The controller is coupled to the switch-capacitor circuit and the output of the amplifier. The controller is configured to switch the switch-capacitor circuit between the sampling mode and the amplification mode, control the amplification mode to have various durations, and determine the bandwidth of the amplifier based on the various durations of the amplification mode and corresponding voltages at the output of the amplifier.

Abstract: A three-dimensional serial focused intraoral digital tomosynthesis scanner includes a frame body, an image capturing module, a photosensitive member and an image processing module. The frame body includes a central axis and a light source seat which is moved along a scanning path and rotated around the central axis. The image capturing module is disposed on the light source seat and reciprocated along the scanning path. The image capturing module is configured to generate a light beam emitted from an outside to the patient's mouth. The photosensitive member is positioned in the patient's mouth. The light beam is emitted to the photosensitive member and moved along the scanning path corresponding to the photosensitive member so as to generate a plurality of two-dimensional optical images by the image capturing module. The image processing module calculates the two-dimensional optical images to generate a three-dimensional image.