Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.

Abstract: A device comprising a device under test and a time to current converter configured to be coupled to the device under test. The device under test comprises: (i) at least one delay element for creating a delay; (ii) at least one capacitor for providing capacitance loading to the at least one delay element; and (iii) at least one switch to control the capacitance loading provided by the at least one capacitor. The time to current converter comprises (i) a first input for receiving a first clock signal; (ii) a second input for receiving an inverted and delayed version of the first clock signal from the device under test; and (iii) an impedance module for measuring an output current. During a testing mode, the at least one switch is in a closed position so the at least one capacitor can provide a capacitance loading to the at least one delay element to amplify the delay associated with the device under test.

Abstract: In certain embodiments, the present disclosure provides compounds and methods of increasing the amount or activity of a target protein in a cell. In certain embodiments, the compounds comprise a translation suppression element inhibitor. In certain embodiments, the translation suppression element inhibitor is a uORF inhibitor. In certain embodiments, the uORF inhibitor is an antisense compound.

Abstract: A display device including a display panel and a backlight module is provided. The backlight module is correspondingly disposed below the display panel and includes light-emitting elements providing light beams and disposed on a circuit board, lens units each being disposed on a corresponding light-emitting element and having a concave inside surface covering the corresponding light-emitting element and a convex outside surface covering the concave inside surface, and an inverse prism sheet disposed between the lens units and the display panel, and the inverse prism sheet having inverse prisms with a vertex corner. At least a portion of the light beams emitted from the convex outside surface each has a predetermined light-emitting angle ?o larger than 30 degrees and less than 90 degrees. The backlight module has a height of cavity D being a distance between the vertex corner and the circuit board, and 10 ?m?D<30 mm.

Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.

Abstract: A driving circuit of a display panel and a display apparatus using the same are provided. The driving circuit includes a shift register, a latch, a level shifter, a current source and a charge switch. The shift register receives a trigger signal to provide a data latch signal. The latch couples to the shift register, and receives a gray-level data to latch and output the gray-level data according to the data latch signal. The level shifter couples to the latch and provides a charge switch signal according to the gray-level data. The current source provides a charge current. The charge switch couples between the current source and a pixel of the display panel, and receives the charge switch signal to determine whether the current source is coupled to the pixel according to the charge switch signal.

Abstract: A decoding method for audio video stream synchronization is provided. The audio video stream includes multiple clock references and multiple audio and video data packets. Each of the data packets corresponds to a presentation value. The decoding method includes: reconstructing a clock value according to a first clock reference; determining whether a difference between the clock value and a first presentation value in multiple presentation values is greater than a first range; when the difference between the clock value and the first presentation value is greater than the first range, changing the clock value to a second presentation value in the multiple presentation values; and performing at least one audio video synchronization step according to the clock value set based on the second presentation value.

Abstract: A cell culture carrier module, a bioreactor and a cell recovery method are provided. The cell culture carrier module includes at least one cell culture carrier capable of transforming between a two dimensional structure and a three dimensional structure. The cell culture carrier exhibits the two dimensional structure in a loosened state and exhibits the three dimensional structure in a compressed state.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges.

Abstract: A backlight module and a display apparatus are provided. The backlight module comprises a back plate, a light source and at least one light-permeable element. The light source disposed on the back plate has at least one light emitting element. The light-permeable element covers the light emitting element, which comprises a light input surface and a light output surface disposed opposite the light input surface. The light input surface faces the light emitting element and has an apex away from the light emitting element. When viewed from a cross section crossing the apex and perpendicular to the back plate, the light input surface has a first curve and a second curve connected to the first curve. A connection point between the first curve and the second curve is an inflection point.

Abstract: A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.

Abstract: A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.

Abstract: The present invention discloses a keyboard device. The keyboard device includes a sheet, a membrane switch, an actuating component, and a protrusion keycap structure. The membrane switch is disposed on a side of the sheet. The actuating component is disposed on a side of the membrane switch far away from the sheet and is for pressing the membrane switch to actuate the membrane switch. The protrusion keycap structure is disposed on a side of the actuating component far away from the membrane switch and is for driving the actuating component to actuate the membrane switch upon being pressed. The protrusion keycap structure includes a mylar film.

Abstract: The present invention presents methods for making oxidation-resistant and wear-resistant polyethylenes and medical implants made therefrom. Preferably, the implants are components of prosthetic joints, e.g., a bearing component of an artificial hip or knee joint. The resulting oxidation-resistant and wear-resistant polyethylenes and implants are also disclosed.

Abstract: An image sensor includes a pixel unit and a pixel readout circuit. The pixel unit includes an image pixel array including a plurality of image pixel columns, respectively; a first reference pixel array including a plurality of first reference pixel columns; and a bias circuit, coupled to the image pixel columns for generating a plurality of column sensing signals, coupled to the first reference pixel columns for generating a plurality of first reference signals, and further for generating a first average reference voltage signal according to the plurality of first reference signals. The pixel readout circuit generates a plurality of reset values and a plurality of sampling values according to the column sensing signals and the first average reference voltage signal, wherein the plurality of reference pixel rows is less than the plurality of image pixel rows.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.