Patents by Inventor Wen Sung

Wen Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014143
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.
    Type: Application
    Filed: June 8, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Lin TSAI, Kun-Ting HUNG, Yin-Fa CHEN, Chi-Yuan CHEN, Wen-Sung HSU
  • Publication number: 20230422525
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Che-Hung Kuo, Hsing-Chih Liu, Tai-Yu Chen, Shih-Chin Lin, Wen-Sung Hsu
  • Patent number: 11854930
    Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: December 26, 2023
    Assignee: MediaTek Inc.
    Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
  • Patent number: 11854784
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: December 26, 2023
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 11837552
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 5, 2023
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Publication number: 20230387075
    Abstract: A semiconductor package includes an interposer over a substrate that includes interconnect traces, a redistribution structure on the interposer, a first semiconductor structure, a second semiconductor structure and a third semiconductor structure on the redistribution structure. The first semiconductor structure includes a first semiconductor die and a first encapsulant that encapsulates the first semiconductor die. The second semiconductor structure includes a second semiconductor die and a second encapsulant that encapsulates the second semiconductor die. The third semiconductor structure is disposed adjacent to a corner or an edge of the substrate in a top plan view of the substrate. The third semiconductor structure includes a third semiconductor die and a third encapsulant that encapsulates the third semiconductor die. The third semiconductor structure is electrically insulated from the substrate, the first semiconductor structure and the second semiconductor structure.
    Type: Application
    Filed: April 20, 2023
    Publication date: November 30, 2023
    Inventors: Yi-Lin TSAI, Wen-Sung HSU, Nai-Wei LIU
  • Patent number: 11830851
    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 28, 2023
    Assignee: MediaTek Inc.
    Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
  • Patent number: 11813123
    Abstract: Ultrasound imaging is a non-invasive, non-radioactive, and low cost technology for diagnosis and identification of implantable medical devices in real time. Developing new ultrasound activated coatings is important to broaden the utility of in vivo marking by ultrasound imaging. Ultrasound responsive macro-phase segregated micro-composite thin films were developed to be coated on medical devices composed of multiple materials and with multiple shapes and varying surface area. The macro-phase segregated in films having silica micro-shells in polycyanoacrylate produces strong color Doppler signals with the use of a standard clinical ultrasound transducer. Electron microscopy showed a macro-phase separation during slow curing of the cyanoacrylate adhesive, as air-filled silica micro-shells were driven to the surface of the film. The air sealed in the hollow space of the silica shells acted as an ultrasound contrast agent and echo decorrelation of air exposed to ultrasound waves produces color Doppler signals.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 14, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Jian Yang, Alexander Liberman, James Wang, Christopher Barback, Natalie Mendez, Erin Ward, Sarah Blair, Andrew C. Kummel, Tsai-Wen Sung, William C. Trogler
  • Patent number: 11791266
    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: October 17, 2023
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11786594
    Abstract: A spiky metal organic framework is provided in the present disclosure. The spiky metal organic framework is formed by a coordination reaction between at least one metal ion and an organic ligand, and includes a body and a plurality of spike-like structures. The body is a spherical shape, and a particle size of the body is 1 ?m to 3 ?m. The spike-like structures are distributed on a surface of the body, a diameter of each spike-like structure is 15 nm to 35 nm, and a length of each spike-like structure is 250 nm to 400 nm.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 17, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hsing-Wen Sung, Po-Ming Chen, Wen-Yu Pan, Yang-Bao Miao, Po-Kai Luo
  • Publication number: 20230322115
    Abstract: A detection circuit for control pilot abnormality of a DC charging pile, which is electrically connected to a control pilot signal generating circuit and a control circuit, providing instant protection for the DC charging pile while control pilot (CP) abnormality been detected. The detection circuit includes a control pilot (CP) signal potential discrimination module, a charging-discharging module electrically connected to the CP signal potential discrimination module, and a controller protection triggering module electrically connected to the charging-discharging module, wherein the CP signal potential discrimination module justifies the voltage level of the input CP signals been input, activates the charging-discharging module to charge the CP signals to a steady-state voltage higher than a predetermined voltage level within a certain time period, and activates the controller protection trigger module to provide instant protection for the DC charging pile.
    Type: Application
    Filed: May 1, 2022
    Publication date: October 12, 2023
    Inventors: Sheng-Wen Sung, Jian-Hsieng Lee, Chun-Chen Chen
  • Publication number: 20230307316
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface. A semiconductor device is mounted on the top surface of the substrate. The semiconductor device has an active front surface directly facing the substrate, and an opposite rear surface. A vapor chamber lid is in thermal contact with the rear surface of the semiconductor device. The vapor chamber lid includes an internal vacuum-sealed cavity that stores a working fluid, and wick structures for recirculating the working fluid within the internal vacuum-sealed cavity.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chin-Lai Chen, Wei-Che Huang, Wen-Sung Hsu, Chun-Yin Lin, Li-Song Lin, Tai-Yu Chen
  • Publication number: 20230307421
    Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Tai-Yu Chen, Che-Hung Kuo, Hsing-Chih Liu, Shih-Chin Lin, Wen-Sung Hsu
  • Patent number: 11755043
    Abstract: A biologically temperature-controlled electronics shell component is adapted to constitute an outer shell and/or a middle shell of an electronic product such as a mobile phone, a tablet device, a laptop computer a wearable device, and the like. A heat source is provided in the electronic product. The shell component includes an outer shell body and an outer heat-conducting sheet. The outer shell body includes at least one hole extending through inner and outer surfaces thereof. The outer heat-conducting sheet corresponding to the heat source and combined with the outer shell body includes a heat-conducting portion corresponding to the hole. Radiant heat generated by the heat source can be absorbed by and dissipated through the outer heat-conducting sheet and conducted through a user's skin which is contacting the heat-conducting portion.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: September 12, 2023
    Inventor: Wen-Sung Hu
  • Publication number: 20230282626
    Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.
    Type: Application
    Filed: February 2, 2023
    Publication date: September 7, 2023
    Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
  • Publication number: 20230284403
    Abstract: The present invention discloses a smart clothing and its device mount, wherein the device mount includes an upper casing and a lower casing, a circuit board is arranged between the upper casing and the lower casing, and a metal contact of the top surface of the circuit board penetrates through the upper casing to form a plurality of metal contact points, and the cable interface of the bottom surface of the circuit board passes through the lower casing, and the bottom surface of the lower casing is formed with individual cable grooves toward each cable interface for guiding the transmission wire to insert into the cable interface along the cable groove, and the device mount is combined with a soft gasket on the clothing body and is equipped with a waterproof protective layer to avoid damage to the circuit components and transmission wire during cleaning; when the device mount is installed with the electronic device, the motion status can be monitored.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 7, 2023
    Inventors: Wen-Sung FAN, Kai-Yuan CHENG, Chih-Wei TU, Pei-Wen LIAO, Ming-Hui YAO, Tzong-Yow HO
  • Publication number: 20230282625
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.
    Type: Application
    Filed: February 9, 2023
    Publication date: September 7, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Shih-Chin Lin, Tai-Yu Chen, Bo-Jiun Yang, Bing-Yeh Lin, Yung-Cheng Huang, Wen-Sung Hsu, Bo-Hao Ma, Isabella Song
  • Patent number: 11751304
    Abstract: A LED feedback voltage regulating driving device is provided. The LED feedback voltage regulating driving device includes a microcontroller, a first feedback circuit, a second feedback circuit, an oscillating circuit and a comparison circuit. The first feedback circuit and the second feedback circuit adjust the voltage and current from the electricity supply module and the driving circuit respectively, and transmit the voltage and current to the microcontroller; wherein, the microcontroller and the oscillating circuit reciprocate the voltage and current from the first feedback circuit and the second feedback circuit; wherein the comparison circuit compares the signal from the microcontroller and the oscillating circuit; wherein the pulse circuit adjusts the voltage and the current then transmits the voltage and current to the driving circuit for electricity driving; wherein, during the electricity driving, the driving circuit transmits part of the voltage and current to the second feedback circuit.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: September 5, 2023
    Inventor: Wen-Sung Lee
  • Patent number: 11742564
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Tzu-Hung Lin, Wen-Sung Hsu
  • Publication number: 20230260866
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 17, 2023
    Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU