Abstract: A service providing apparatus, a service consuming apparatus, and a service transmitting method are provided. The service providing apparatus is adapted to connect with the service consuming apparatus via a wireless network. Within a control channel period, the service providing apparatus schedules the services with the service consuming apparatus. Within a service channel period, the service providing apparatus provides a service resource to the service consuming apparatus according to the result of scheduling the services. If the service consuming apparatus does not send a service request signal to the service providing apparatus within the control channel period, the service consuming apparatus has to remain silent within the service control channel. By the arrangement, the problems caused from the characteristic of the link asymmetry of the wireless network can be solved.

Abstract: A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: A low complexity and low power phase shift keying demodulator structure includes a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler. The digitizer digitizes a BPSK signal for an output waveform. The phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal. The binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor. The sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only a small capacitance.

Abstract: A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out stored in. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

Abstract: The present invention relates to a blood flow simulation system, which comprises a first container, a phantom, and a second container. The blood flow simulation system according to the present invention contains a fluid by the first container. Then the phantom is used for transporting the fluid. Afterwards, the second container is used for containing the fluid output by the phantom, and transporting the fluid to the first container by way of the phantom. Thereby, the blood-vessel characteristics, the blood-flow characteristics, and the human muscle characteristics can be simulated effectively and hence facilitating experimental convenience.

Abstract: A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

Abstract: A method for improving alignment in a photolithography machine is provided. The method comprises identifying first empirical alignment data that has been determined from use of a target photomask within at least one non-target tool, and identifying second empirical alignment data that has been determined from use of a non-target photomask within a target tool. The method continues by identifying third empirical alignment data that has been determined from use of a non-target photomask within at least one non-target tool, and calculating from the first, second, and third empirical alignment data a predicted alignment data for the target photomask with the target tool. The method then proceeds by aligning the target photomask within the target tool using the predicted alignment data, exposing a pattern from the target photomask onto the wafer in the target tool, and further processing the exposed wafer.

Abstract: A low complexity and low power phase shift keying demodulator structure comprises: a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler; wherein the digitizer digitizes a BPSK signal for an output waveform, the phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal, the binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor, the sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only small capacitance.

Abstract: System and method for automated semiconductor manufacturing is provided. In accordance with one aspect of the present invention, a system for automated semiconductor wafer manufacturing includes a smart overlay control (SOC) database having empirical alignment data related to overlay alignment, and a simulation module communicatively coupled to the SOC database, the simulation module determining a simulated overlay alignment of a wafer on the plurality of photolithography tools in a tool bank based on the empirical alignment data stored in the SOC database. The system also includes a dispatch module communicatively coupled to the SOC database and the simulation module, the dispatch module controlling the dispatch of a wafer to one of a plurality of photolithography tools in a tool bank based at least in part on the simulated overlay alignment.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.

Abstract: The present invention provides biomarkers for detecting kidney disease, selected from the oligonucleotide sequence, complementary sequence or derivatives, amino acid sequence or derivatives, fragment, variants, antibody of annexin A2 or S100A6 or combinations thereof. Moreover, the present invention also provides an assay kit and a method for kidney disease detecting, practically for the kidney disease resulting from acute tubular necrosis.

Abstract: A cigarette lighter adapter with USB connector, includes a first casing engagable with a second casing, the first and the second casings cooperatively defining a plug portion and a holding portion, a circuit board, a contact terminal, a fixed spring contact, a USB connector having an insertion opening, a rotating means, and a transmission wire electrically connected to the circuit board, wherein a sleeve having a plug hole corresponding to the insertion opening is mounted to the engaged first and the second casings and is able to rotate about the holding portion by means of the rotating means to locate the plug hole facing the insertion opening in an insertion position or to shield the insertion opening, whereby to protect the USB connector and keep dust out of the USB connector.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: The invention provides a method of repairing the pixel structure, and the method includes the following. First, an electrical connection between the current control unit and the power line is cut. The power line is then electrically connected to the redundant active device, so that the current control unit and the redundant active device control the current provided by the power line. The invention provides a method of repairing the organic electro-luminescence display unit, suitable for repairing the above-mentioned organic electro-luminescence display unit, and the method includes the following. First, an electrical connection between the current control unit and the power line is cut. The power line is electrically connected to the redundant active device, so that the current control unit and the redundant active device control the current passing through the organic electro-luminescence layer.

Abstract: A pixel structure electrically connected to a scan line, a data line and a power line is provided. The pixel structure includes a current control unit, a pixel electrode and a redundant active device. The current control unit is electrically connected to the scan line, the data line and the power line. The pixel electrode is electrically connected to the current control unit. The redundant active device is electrically connected to the pixel electrode and the current control unit, and the redundant active device is electrically insulated from the power line. Moreover, an organic electro-luminescence displaying unit and a repairing method thereof are further provided.

Abstract: A method of fabricating a TFT array substrate and a metal layer thereof is provided. First, a substrate having a first patterned metal layer disposed thereon is provided, wherein the first patterned metal layer is formed by an electroplating method. Then, a gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the first metal layer. Next, a semiconductive layer is formed on the gate insulating layer over the first metal layer. Then, a patterned second metal layer is formed on the semiconductive layer. The first metal layer, the second metal layer and the semiconductive layer constitute a plurality of thin film transistors, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are coupled to the thin film transistors.

Abstract: A method of evaluating and optimizing performance of a chiller system includes the following steps. Determine a number of activated chillers, a number of activated cooling towers, and the lowest outlet temperature of cooling water of a cooling tower as an operating settings. By developing evaluating models, sequentially determine a temperature of the cooling water entering the chillers, a total power consumption of chillers, a total power consumption of the cooling towers, and a total power consumption of pumping cooling water. Then, determine a total power consumption of the system by the sum of the total power consumption of the chillers, the total power consumption of the cooling towers, and the total power consumption of pumping cooling water. Through the above method, the system total power consumptions under different operating settings are evaluated, so as to determine an optimized operating setting to optimize the performance of the system.

Abstract: A communication system adapted to be connected to a calling device through the Internet includes a proxy device and a plurality of communication devices. The proxy device receives messages sent from the calling device through the Internet. Each of the communication devices has specific media processing capability, and receives the messages sent by the calling device through the proxy device and the Internet. The proxy device and the communication devices store the media processing capabilities of the communication devices, and upon receipt of a message requesting connection from the calling device, select one of the communication devices with the media processing capability matching that required by the connection according to the media processing capabilities of the communication devices stored therein. The selected communication device sets up a connection with the calling device through the proxy device, or selects another communication device to set up the connection.