Abstract: A method of fabricating a semiconductor device includes providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.

Abstract: An immersion cooling system includes a tank, a first condenser, an enclosure, a second condenser and a connecting pipe. The tank has a first space. The first space is configured to accommodate a cooling liquid for at least one electronic equipment to immerse therein. The first condenser is disposed inside the tank. The enclosure is disposed outside the tank. The enclosure forms a second space together with the tank. The second condenser is disposed in the second space. The connecting pipe includes a first end and a second end opposite to the first end. The first end is connected with the second condenser. The second end is communicated with the first space.

Abstract: The present disclosure provides a method and an electronic apparatus for masking data on an electronic document. The method is performed by the electronic apparatus and includes: displaying the electronic document on a user interface; causing at least one analysis module to perform at least one analysis on the electronic document and a plurality of strings of the electronic document and output a first string among the plurality of strings and first position information associated with the first string according to a result of the at least one analysis; obtaining the first string and the first position information from the at least one analysis module; and generating, based on the first position information and the first string, a first masking object to mask the first string on the electronic document.

Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.

Abstract: An embodiment semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region over a surface of the package substrate and the capillary underfill material may be formed over a second region of the surface of the package substrate, such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame partially surrounding the first semiconductor die and the second semiconductor die such that a multi-die chip is formed that includes the first semiconductor die, the second semiconductor die, and the multi-die frame.

Abstract: A transmission method for increasing a transmission throughput of a communication device includes: receiving a wireless signal, wherein the wireless signal includes a received packet; determining whether the received packet is from an overlapping basic service set (OBSS), and determining a length of a duration of a transmission opportunity (TXOP) according to information carried by the received packet; in response to the received packet being from the OBSS, performing packet transmission in a spatial reuse manner within the duration of the TXOP; and performing the packet transmission in a general manner after the duration of the TXOP ends; wherein a transmission power utilized in the spatial reuse manner is different from a transmission power utilized in the general manner, and a plurality of packets are transmitted in the spatial reuse manner within the duration of the TXOP.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.

Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A package structure is provided. The package structure includes a substrate and a ground structure laterally surrounded by the substrate. The package structure also includes a chip-containing structure over the substrate and a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The ground structure is electrically connected to the protective lid through the first adhesive element. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: An optical device is provided. The optical device includes a first photonic component and a second photonic component. The first photonic component is configured to communicate with the second photonic component through a first optical path or an electrical path depending on a distance between the first photonic component and the second photonic component.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Abstract: A package structure includes a package substrate, a semiconductor die module on the package substrate, a ring structure on the package substrate adjacent to the semiconductor die module, and a hybrid adhesive having a first modulus and a second modulus less than the first modulus and attaching the ring structure to the package substrate.

Abstract: An artificial leather and a method for manufacturing the artificial leather are provided. The artificial leather includes a fabric layer, a thermoplastic polyolefin layer, a modified thermoplastic polyolefin layer, and a polyurethane surface layer. The thermoplastic polyolefin layer is disposed on the fabric layer. The modified thermoplastic polyolefin layer is disposed on the thermoplastic polyolefin layer. The polyurethane surface layer is attached to the modified thermoplastic polyolefin layer through an adhesive.

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Abstract: A wireless communication method for optimizing uplink transmission from a communication partner to a wireless communication device includes the following steps: after receiving an uplink performance estimation, determining uplink adjustment information including resource unit allocation and a target received signal strength indicator according to the uplink performance estimation; generating a target channel quality indicator (CQI) according to previous uplink sounding information and the uplink adjustment information, wherein the previous uplink sounding information indicates the characteristics of the uplink transmission; determining uplink transmission setting including a modulation and coding scheme and dual carrier modulation according to the target CQI and the type of an error correction technique and transmitting a control signal to a communication partner according to the uplink transmission setting; and updating the uplink performance estimation according to a reception signal from the communication