Patents by Inventor Wen-Yi Lin

Wen-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11353925
    Abstract: The present disclosure discloses a portable electronic device including a primary display panel, a keyboard module, a secondary display panel, and a support plate. The primary display panel includes a first pivot and a second pivot. The first pivot and the second pivot are disposed at the primary display panel. The keyboard module faces the primary display panel and includes a third pivot. One side of the secondary display panel is connected to the first pivot, and another side is a free side. The secondary display panel is flipped through the first pivot to be overlapped on an upper surface of the keyboard module or to abut against the upper surface at the free side. The support plate is flipped through the second pivot and the third pivot to be overlapped on the bottom surface of the primary display panel or to support the primary display panel.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: June 7, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Shih-Yao Lin, Tsung-Cheng Lin, Wen-Chung Wu, Tao-Hua Cheng, Pei-Yi Lee, Chia-Liang Chiang
  • Patent number: 11344894
    Abstract: A tramp metal separation assembly comprises a housing, a core rod and a sleeve tube. The housing includes a first and second discharging areas and a feeding area. The core rod includes a first and second non-magnetic sections and a magnetic section. The core rod is mounted on the housing in a way that the first and second non-magnetic sections correspond respectively to the first and second discharging areas and the magnetic section corresponds to the feeding area. The sleeve tube includes a first and second portions. The sleeve tube is sleeved outside the core rod in a way that it is moveable between a first position, wherein the first portion corresponds to the magnetic section and the second portion corresponds to the second non-magnetic section, and a second position, wherein the first portion corresponds to the first non-magnetic section and the second portion corresponds to the magnetic section.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: May 31, 2022
    Assignee: TAI HAN EQUIPMENT ENTERPRISE CO., LTD.
    Inventors: Shyh-Yi Wey, Wen-Cheng Chang, Ken-Der Lin, Bao-Ding Li
  • Publication number: 20220155161
    Abstract: A medicament delivery device development evaluation system is presented having a dummy medicament delivery device comprising at least one force sensor configured to detect an external force applied to the dummy medicament delivery device, processing circuitry configured to receive force measurements from the force sensor, and a storage medium configured to store the force measurements received by the processing circuitry.
    Type: Application
    Filed: February 13, 2020
    Publication date: May 19, 2022
    Inventors: Chun Chang, Chia Cheng Lin, Sheng-wei Lin, Hsueh-Yi Chen, Yiju Chen, Wen-Sheng Chien
  • Publication number: 20220157472
    Abstract: A method for enhancing an accuracy of a benign tumor development trend assessment system includes: a first processing procedure, an image captured before the treatment is inputted to and be processed by a server computing device of the benign tumor development trend assessment system to obtain a first processing result; a second processing procedure, the images captured before and in at least one period after the treatment are inputted to and processed by the server computing device to obtain a second processing result; a trend analyzing procedure, the trend analyzing module of the server computing device analyzes the first processing result, the second processing result and the trend pathways to obtain a tumor development trend result; and a storing procedure, the first processing result, the second processing result and the tumor development trend result are transformed to an individual trend pathway which is stored in the trend analyzing module.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: CHENG-CHIA LEE, HUAI-CHE YANG, WEN-YUH CHUNG, CHIH-CHUN WU, WAN-YUO GUO, WEI-KAI LEE, TZU-HSUAN HUANG, CHUN-YI LIN, CHIA-FENG LU, YU-TE WU
  • Publication number: 20210272869
    Abstract: A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Patent number: 11011447
    Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Shin-Puu Jeng, Wen-Yi Lin, Shu-Shen Yeh
  • Patent number: 10790164
    Abstract: A method for forming a package structure is provided. The method includes forming a first die over a first substrate, and injecting a molding compound material from a first side of the first die to a second side of the first die. The molding compound material includes a plurality of first fillers, each of the first fillers has a length along a longitudinal axis and a width along a transverse direction, and the length is greater than the width. The method further includes heating the molding compound material to form a package layer over the first die, and the first fillers are substantially parallel to each other.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Yi Lin, Che-Chia Yang, Kuang-Chun Lee, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20200058571
    Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.
    Type: Application
    Filed: February 14, 2019
    Publication date: February 20, 2020
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Patent number: 10361190
    Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 23, 2019
    Assignee: MEDIATEK INC.
    Inventors: Kin-Hooi Dia, Hugh Thomas Mair, Shao-Hua Huang, Wen-Yi Lin
  • Patent number: 10305480
    Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: May 28, 2019
    Assignee: MEDIATEK INC.
    Inventor: Wen-Yi Lin
  • Patent number: 10269602
    Abstract: The present disclosure provides a system for wafer warpage inspection including a heatable susceptor configured to heat a wafer according to a predetermined temperature profile. The system for wafer warpage inspection further includes a confocal imager array over the heatable susceptor configured to capture one or more warpage parameters of the wafer. Each confocal imager of the confocal imager array covers a predetermined field of view (FOV). The system for wafer warpage inspection further includes a first actuator permitting the confocal imager array to move in a plurality of directions. The system for wafer warpage inspection further includes a processing unit connected to the confocal imager array. The processing unit is configured to dynamically process the one or more warpage parameters captured during the heating of the wafer according to the predetermined temperature profile. Present disclosure also provides a method for wafer warpage inspection described herein.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Yi Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20190055435
    Abstract: A protective film includes a protective layer, an adhesive layer, and a releasing layer. The protective layer, the adhesive layer, and the releasing layer are stacked together in that order. The adhesive layer includes a pressure-sensitive adhesive in an amount by weight of about 90 parts to about 100 parts, inorganic fluorescent powders in an amount by weight of about 0.05 parts to about 0.5 parts, and a curing agent in an amount by weight of about 0.5 parts to about 3 parts.
    Type: Application
    Filed: May 25, 2018
    Publication date: February 21, 2019
    Inventor: WEN-YI LIN
  • Patent number: 10126363
    Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Wen-Yi Lin, Girishankar Gurumurthy
  • Publication number: 20180224505
    Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.
    Type: Application
    Filed: July 12, 2017
    Publication date: August 9, 2018
    Inventors: Wen-Yi LIN, Girishankar GURUMURTHY
  • Patent number: 9887144
    Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi Lin, Yu-Chih Liu, Ming-Chih Yew, Tsung-Shu Lin, Bor-Rung Su, Jing Ruei Lu, Wei-Ting Lin
  • Patent number: 9881908
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 9748156
    Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Shen Yeh, Cheng-Lin Huang, Chin-Hua Wang, Kuang-Chun Lee, Wen-Yi Lin, Ming-Chih Yew, Yu-Huan Chen, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 9721868
    Abstract: A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yao Lin, Wen-Yi Lin, Shyue Ter Leu, Ming-Chih Yew, Shu-Shen Yeh
  • Patent number: D832839
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 6, 2018
    Assignee: Darwin Precisions Corporation
    Inventors: Yu-Tsung Su, Wen-Yi Lin
  • Patent number: D834575
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 27, 2018
    Assignee: Darwin Precisions Corporation
    Inventors: Yu-Tsung Su, Wen-Yi Lin