Patents by Inventor Wen-Yi Lin

Wen-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387272
    Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Inventors: Zhen-Nong Wu, Mao-Chia Wang, Jia-Ren Chen, Li-Yi Chen, Wen Han Hung, Che-Li Lin, Yen-Ning Chen
  • Publication number: 20240386180
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 12150066
    Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: November 19, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Zh-Hong Xiao, Shau-Yu Cheng, Wen-Yung Lee, Chun-Kai Tseng, Jhe-Yi Lin
  • Publication number: 20240379475
    Abstract: A package structure is provided. The package structure includes a substrate and a ground structure laterally surrounded by the substrate. The package structure also includes a chip-containing structure over the substrate and a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The ground structure is electrically connected to the protective lid through the first adhesive element. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chen-Shien CHEN
  • Publication number: 20240379488
    Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Publication number: 20240379670
    Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
  • Publication number: 20240379584
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20240345337
    Abstract: An optical device is provided. The optical device includes a first photonic component and a second photonic component. The first photonic component is configured to communicate with the second photonic component through a first optical path or an electrical path depending on a distance between the first photonic component and the second photonic component.
    Type: Application
    Filed: April 14, 2023
    Publication date: October 17, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tai-Hsiang LIU, Hung-Yi LIN, Wen Chieh YANG
  • Patent number: 12119276
    Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chen-Shien Chen
  • Publication number: 20240328078
    Abstract: An artificial leather and a method for manufacturing the artificial leather are provided. The artificial leather includes a fabric layer, a thermoplastic polyolefin layer, a modified thermoplastic polyolefin layer, and a polyurethane surface layer. The thermoplastic polyolefin layer is disposed on the fabric layer. The modified thermoplastic polyolefin layer is disposed on the thermoplastic polyolefin layer. The polyurethane surface layer is attached to the modified thermoplastic polyolefin layer through an adhesive.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Inventors: CHIH-YI LIN, Kuo-Kuang Cheng, Chien-Chia Huang, Chi-Chin Chiang, Wen-Hsin Tai, Chieh Lee, Yu-Lun Chen, Yu Hung Liu
  • Publication number: 20240332212
    Abstract: A package structure includes a package substrate, a semiconductor die module on the package substrate, a ring structure on the package substrate adjacent to the semiconductor die module, and a hybrid adhesive having a first modulus and a second modulus less than the first modulus and attaching the ring structure to the package substrate.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Inventors: Wen-Yi Lin, Yi-Che Chiang, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20240324474
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE
  • Patent number: 12101175
    Abstract: A wireless communication method for optimizing uplink transmission from a communication partner to a wireless communication device includes the following steps: after receiving an uplink performance estimation, determining uplink adjustment information including resource unit allocation and a target received signal strength indicator according to the uplink performance estimation; generating a target channel quality indicator (CQI) according to previous uplink sounding information and the uplink adjustment information, wherein the previous uplink sounding information indicates the characteristics of the uplink transmission; determining uplink transmission setting including a modulation and coding scheme and dual carrier modulation according to the target CQI and the type of an error correction technique and transmitting a control signal to a communication partner according to the uplink transmission setting; and updating the uplink performance estimation according to a reception signal from the communication
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: September 24, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Yung Lee, Shau-Yu Cheng, Jhe-Yi Lin, Chun-Kai Tseng, Wei-Hsuan Chang
  • Publication number: 20240302410
    Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Inventors: Wen-Yi LIN, Hao CHEN, Chuan-Hsiang SUN, Mill-Jer WANG, Chien-Chen LI, Chen-Shien CHEN
  • Publication number: 20240290683
    Abstract: An embodiment semiconductor package structure may include a package substrate, a semiconductor die coupled to the package substrate, and a package lid attached to the package substrate and covering the semiconductor die. The package lid may include a top portion having a spatially varying thermal conductivity that is greater in a first region than in a second region. The first region may include a multi-layer structure including a metal/diamond composite material supported by a copper layer. The metal/diamond composite material may include a silver/diamond, copper/diamond, or aluminum/diamond material and may have a thermal conductivity that is within a range from 600 W/m·K to 900 W/m·K and a coefficient of thermal expansion that is in a second range from 5 ppm/° C. to 10 ppm/° C. The package lid may have an effective coefficient of thermal expansion that is in a range from 14.5 ppm/° C. to 17 ppm/° C.
    Type: Application
    Filed: February 27, 2023
    Publication date: August 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240272318
    Abstract: A neutron measuring method is provided. The method includes utilizing the thermoluminescent crystal in the thermoluminescent dosimeter to convert the ionizing radiation emitted by an activated metallic body into scintillation light. The method further includes using a photodetector to measure the intensity of the scintillation light. The method further includes calculating the activity of the metallic body based on the intensity of the scintillation light and the second conversion factor. The method further includes using the second conversion formula to calculate the neutron intensity at the location of the metallic body based on the calculated activity of the metallic body.
    Type: Application
    Filed: June 13, 2023
    Publication date: August 15, 2024
    Applicant: Heron Neutron Medical Corp.
    Inventors: Wen-Chyi Tsai, Tzung-Yi Lin
  • Publication number: 20240260183
    Abstract: The present disclosure is relates to a conductive film and a manufacturing method thereof. The conductive film includes a base layer, a TPU complex layer, a conductive layer and a TPU surface layer. The TPU complex layer includes a TPU heat-resistant layer and a TPU melting layer. The TPU heat-resistant layer is disposed on the TPU melting layer, and the TPU melting layer is disposed on the base layer. The conductive layer includes a conductive circuit disposed on the TPU heat-resistant layer. The TPU surface layer is disposed on the conductive layer. Utilizing the TPU complex layer, the conductive layer does not contact directly with the base layer to avoid breaking the conductive line of the conductive layer when the base layer is pulled. Therefore, the lifetime of the conductive film can be increased.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chi-Chin Chiang, Wen-Hsin Tai, I-Ju Wu, Chi-Ho Tien
  • Patent number: 12041860
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Wen-Zhang Lin, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Chrong-Jung Lin, Ya-Chin King, Cheng-Jun Lin, Wang-Yi Lee
  • Publication number: 20240230323
    Abstract: A method of inspecting flatness of substrate is provided and includes providing a substrate. N first inspecting points are selected from the surface of the substrate along a first straight line, where the coordinate of the i-th first inspecting point is (Xi,Yi,Zi). By using a formula “ D = ? i = 1 N - 1 ? ( X i + 1 - X i ) 2 + ( Y i + 1 - Y i ) 2 + ( Z i + 1 - Z i ) 2 ” , a first measurement length D is calculated. By using a formula “F=(D?S)/S”, a first flatness index F is calculated. S is the horizontal distance between 1st first inspecting point and N-th first inspecting point. When the first flatness index F is larger than a first threshold, the substrate is determined to be unqualified.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Chin-Wang HSU, Wen-Yi LIN
  • Patent number: 12024780
    Abstract: A method of preparing a metal mask substrate includes providing a metal substrate. Next, a gloss is measured and obtained from the surface of the metal substrate. Next, the gloss is determined whether to be within a predetermined range. When the gloss is determined within the predetermined range, a photolithography process is performed to the metal substrate, where the predetermined range is between 90 GU and 400 GU.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: July 2, 2024
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Chi-Wei Lin, Wen-Yi Lin