Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.

Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.

Abstract: An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate.

Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.

Abstract: A board-level package includes a printed circuit board, a semiconductor die package mounted on the printed circuit board, a tuned mass structure, and a support structure mounted to the printed circuit board and supporting the tuned mass structure.

Abstract: A semiconductor device includes a substrate, a first die attached to the substrate, and a lid coupled to the substrate. The lid defines a cavity for engaging the first die, and the lid has a die enclosure barrier having ends extending downwardly into the cavity. The ends of the die enclosure barrier are attached to the substrate and a thermal interface material is disposed between the first die and the lid, thermally connecting the first die to the lid.

Abstract: A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

Abstract: A board-level package includes a printed circuit board, a semiconductor die package mounted on the printed circuit board, a tuned mass structure, and a support structure mounted to the printed circuit board and supporting the tuned mass structure.

Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.

Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.

Abstract: An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate.

Abstract: A check valve has a valve body, a piston and a spring. The valve body has a tube, a nozzle and a valve seal. The tube has a sealing protrusion and an inner surface. The sealing protrusion is formed around the inner surface of the tube. The nozzle is combined with the tube and has an insert hole and multiple outlets. The valve seal abuts a shoulder of the sealing protrusion. The piston is mounted in the valve body and has a shaft, a sealing ring and a plug. The shaft is mounted through the insert hole. The sealing ring is mounted in the sealing groove. The plug is a conic frustum and is mounted on a plug end of the shaft. The spring is mounted around the shaft. In operation, the check valve regulates outflow volume under varying pressure to prevent a waste of water.

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.

Abstract: A method for making an optical device includes the steps of: rubbing an orienting film so as to stretch the molecular structure thereof and so as to permit the molecular units of the molecular structure to be aligned along a first axis and to permit the orienting space between each adjacent pair of the molecular units of the molecular structure to be oriented in a direction parallel to a second axis; and forming an optical anisotropical layer on the orienting film by applying a liquid crystal film of rod-like molecules on the orienting film which orients the rod-like molecules by virtue of spatial effect of the molecular units and the orienting spaces.

Abstract: A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.

Abstract: A check valve has a valve body, a piston and a spring. The valve body has a tube, a nozzle and a valve seal. The tube has a sealing protrusion and an inner surface. The sealing protrusion is formed around the inner surface of the tube. The nozzle is combined with the tube and has an insert hole and multiple outlets. The valve seal abuts a shoulder of the sealing protrusion. The piston is mounted in the valve body and has a shaft, a sealing ring and a plug. The shaft is mounted through the insert hole. The sealing ring is mounted in the sealing groove. The plug is a conic frustum and is mounted on a plug end of the shaft. The spring is mounted around the shaft. In operation, the check valve regulates outflow volume under varying pressure to prevent a waste of water.