Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

Abstract: A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units.

Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.

Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.

Abstract: A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units.

Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.

Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.

Abstract: A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.