Abstract: A method of preparing a metal mask substrate includes providing a metal substrate. Next, a gloss is measured and obtained from the surface of the metal substrate. Next, the gloss is determined whether to be within a predetermined range. When the gloss is determined within the predetermined range, a photolithography process is performed to the metal substrate, where the predetermined range is between 90 GU and 400 GU.

Abstract: A method of manufacturing a metal mask includes calendering a metal material, so as to form a metal mask substrate, where the metal mask substrate includes a surface and a plurality of grooves formed in the surface, and the grooves all extend in a direction. The surface has at least one sampling region, while at least two grooves are distributed in the sampling region, where an average area ratio of the area of the grooves within the sampling region to the area of the sampling region ranges between 45% and 68%.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate, and forming a first adhesive element over the substrate. The first adhesive element has a first electrical resistivity. The method also includes forming a second adhesive element over the substrate. The second adhesive element has a second electrical resistivity, and the second electrical resistivity is greater than the first electrical resistivity. The method further includes attaching a protective lid to the substrate through the first adhesive element and the second adhesive element. The protective lid surrounds the chip structure and covers a top surface of the chip structure.

Abstract: A method of inspecting flatness of substrate is provided and includes providing a substrate. N first inspecting points are selected from the surface of the substrate along a first straight line, where the coordinate of the i-th first inspecting point is (Xi,Yi,Zi). By using a formula “D=?i=1N?1?{square root over ((Xi+1?Xi)2+(Yi+1?Yi)2+(Zi+1?Zi)2)}”, a first measurement length D is calculated. By using a formula “F=(D?S)/S”, a first flatness index F is calculated. S is the horizontal distance between 1st first inspecting point and N-th first inspecting point. When the first flatness index F is larger than a first threshold, the substrate is determined to be unqualified.

Abstract: A metal mask and an inspecting method thereof are provided. In the method, a metal mask having a first and a second long side, a first and a second short side, and plural pattern regions is provided. Afterwards, based on the pattern regions adjacent to the first and second long sides, a first reference straight line adjacent to the first long side and a second reference straight line adjacent to the second long side are defined. Then, a first maximum offset length between the pattern regions adjacent to first long side and first reference straight line is measured. A second maximum offset length between the pattern regions adjacent to second long side and second reference straight line is measured. When a difference between the first and second maximum offset lengths is less than or equal to 20 ?m, the metal mask is determined to meet an inspecting standard.

Abstract: A metal backplate is composed of two parallel plain parts and a flexible part lying two plain parts, and the flexible part has a first surface and a second surface deployed underneath the first surface. The flexible part is etched or etched partially with a plurality of curved first openings which form a first array in a staggered arrangement in order to weaken the flexible part B with rigidity property to be one with bending-resilience property; at the same time, which form in staggered rows or in alignments on the upside and the reverse side of the first surface in order to decrease the unidirectional stress concentration and the warpage problem of the display panel.

Abstract: A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.

Abstract: A method for forming a package structure is provided. The method includes forming a first die over a first substrate, and injecting a molding compound material from a first side of the first die to a second side of the first die. The molding compound material includes a plurality of first fillers, each of the first fillers has a length along a longitudinal axis and a width along a transverse direction, and the length is greater than the width. The method further includes heating the molding compound material to form a package layer over the first die, and the first fillers are substantially parallel to each other.

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

Abstract: The present disclosure provides a system for wafer warpage inspection including a heatable susceptor configured to heat a wafer according to a predetermined temperature profile. The system for wafer warpage inspection further includes a confocal imager array over the heatable susceptor configured to capture one or more warpage parameters of the wafer. Each confocal imager of the confocal imager array covers a predetermined field of view (FOV). The system for wafer warpage inspection further includes a first actuator permitting the confocal imager array to move in a plurality of directions. The system for wafer warpage inspection further includes a processing unit connected to the confocal imager array. The processing unit is configured to dynamically process the one or more warpage parameters captured during the heating of the wafer according to the predetermined temperature profile. Present disclosure also provides a method for wafer warpage inspection described herein.

Abstract: A protective film includes a protective layer, an adhesive layer, and a releasing layer. The protective layer, the adhesive layer, and the releasing layer are stacked together in that order. The adhesive layer includes a pressure-sensitive adhesive in an amount by weight of about 90 parts to about 100 parts, inorganic fluorescent powders in an amount by weight of about 0.05 parts to about 0.5 parts, and a curing agent in an amount by weight of about 0.5 parts to about 3 parts.

Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.

Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.

Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.