Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.

Abstract: The invention provides a photoresist coating method, which comprises the following steps: providing a wafer with a pattern on the wafer, placing the wafer on a spinner, injecting a photoresist on a central region of the wafer from a nozzle, and carrying out a spin coating step, the spin coating step comprises: turning on the spinner to rotate the spinner to a first rotation speed, and raising the first rotation speed to a second rotation speed, and performing a plurality of brakes during the process of maintaining the second rotation speed, so that the second rotation speed instantly drops to a third rotation speed, and then rises to the second rotation speed again.

Abstract: A resistor trimming device comprising a resistor trimming unit is provided, which divides a single one adjustable resistor string into a plurality of adjustable resistor string groups, so that a resistance of the parallel resistor faced by a switch can be effectively reduced, and a design of the on-resistance and off-resistance of the switch can comply with a general design rule. In addition, the resistor trimming device provided further comprises a decoder. When trimming the overall resistance of an electronic device, a user can directly input a binary code or an original thermometer code used in the adjustable resistor string being not grouped, without knowing an encoding manner, and then, the decoder generates a trimming thermometer code and a group code to control a main switch and switches in the multiple adjustable resistor string groups being the grouped from the adjustable resistor string.

Abstract: The invention provides a method for detecting the back surface of a wafer, which comprises providing a wafer and performing a detection step on the back surface of the wafer, wherein the detection step comprises capturing a gray scale map of the back surface of the wafer, finding out at least one defect of the back surface of the wafer according to a deviation of the gray scale map, and transmitting the data of the at least one defect back to a system, and the system performs a judgment step according to the data of the at least one defect.

Abstract: An embodiment semiconductor device may include an electrical interconnect layer, a bonding pad electrically coupled to the electrical interconnect layer, a stacked film structure including a first film partially covering a surface of the bonding pad and a second film partially covering the first film, a first aperture formed in the first film over a portion of the surface of the bonding pad, a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, and a solder material portion formed in contact with the bonding pad. The solder material portion may include a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film.

Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms.

Abstract: An approach for protecting container image and runtime data from host access may be presented. Container systems have allowed for more efficient utilization of computing resources, removing the requirement of a hypervisor, and packaging all necessary dependencies within an application. Preventing host access to container image and runtime data can be advantageous for a multitude of reasons. The approach herein may include, flattening a plurality of root file system of a one or more container images into a single layer. The approach may also include generating a container base image for each of the one or more flattened root file system. The approach may include encrypting each of the generated container base images with the flattened root file system.

Abstract: A metal backplate is composed of two parallel plain parts and a flexible part lying two plain parts, and the flexible part has a first surface and a second surface deployed underneath the first surface. The flexible part is etched or etched partially with a plurality of curved first openings which form a first array in a staggered arrangement in order to weaken the flexible part B with rigidity property to be one with bending-resilience property; at the same time, which form in staggered rows or in alignments on the upside and the reverse side of the first surface in order to decrease the unidirectional stress concentration and the warpage problem of the display panel.

Abstract: A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

Abstract: The present disclosure provides a semiconductor memory device and a method of fabricating the same, with the semiconductor memory device including a substrate, a plurality of capacitor structures, a stress insulating layer, and at least one interface layer. The capacitor structures are separately disposed on the substrate, and each of the capacitor structures includes a plurality of capacitors. The stress insulating layer is disposed on the substrate to cover the capacitor structures. The interface layer is disposed within the stress insulating layer, between any two adjacent ones of the capacitor structures, wherein a tip portion of the at least one interface layer is higher than a top surface of each of the capacitor structures. In this way, the stress mode of the substrate may be adjusted through disposing the interface layer, so as to achieve the effect of eliminating redundant stress, and to improve the structural reliability of the device.

Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

Abstract: The present disclosure provides a testkey structure and a monitoring method with a testkey structure, and the testkey structure includes a first diffusion region and a second diffusion region, a first gate and a second gate, a first epitaxial layer and a second epitaxial layer, and an input pad and an output pad. The first diffusion region and the second diffusion region are disposed in a substrate. The first gate and the second gate are disposed on a substrate, across the first diffusion region and the second diffusion region respectively. The first epitaxial layer and the second epitaxial layer are respectively disposed on the second diffusion region and the first diffusion region, separately disposed between the first gate and the second gate. The input pad and the output pad are electrically connected to the first epitaxial layer and the second epitaxial layer respectively.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.

Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate with a photoresist layer, forming a hydrophilic film on a surface of the photoresist layer by a spin coating process, and forming a top anti-reflective coating (TARC) on the surface of the hydrophilic film.

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.