Patents by Inventor Wen-Yuan Chang

Wen-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12227865
    Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Min Lin, Hung-San Lu, Chao-Lung Chen, Chao Yuan Chang, Chun-An Kung, Chin-Hsin Hsiao, Wen-Chun Hou, Szu-Hung Yang, Ping-Ching Jiang
  • Publication number: 20250054857
    Abstract: An integrated circuit (IC) device includes an interlayer dielectric (ILD), first and second tower structures embedded in the ILD, and first and second ring regions including portions of the ILD that correspondingly extend around the first and second tower structures. Each of the first and second tower structures includes a plurality of conductive patterns in a plurality of metal layers, and a plurality of vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of conductive patterns and the plurality of vias are coupled to each other to form the corresponding first or second tower structure. The first ring region extends around the first tower structure, without extending around the second tower structure.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Yu-Jung CHANG, Nien-Yu TSAI, Min-Yuan TSAI, Wen-Ju YANG
  • Publication number: 20240421124
    Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.
    Type: Application
    Filed: September 27, 2023
    Publication date: December 19, 2024
    Applicant: VIA Technologies, Inc.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Publication number: 20240421096
    Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.
    Type: Application
    Filed: September 27, 2023
    Publication date: December 19, 2024
    Applicant: VIA Technologies, Inc.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Publication number: 20220359364
    Abstract: A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.
    Type: Application
    Filed: March 16, 2022
    Publication date: November 10, 2022
    Applicant: VIA Technologies, Inc.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Gao-Tian Lin
  • Patent number: 11227848
    Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 18, 2022
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11081371
    Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 3, 2021
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 10756077
    Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 25, 2020
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10504847
    Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 10, 2019
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10459007
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 29, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Publication number: 20190139898
    Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 9, 2019
    Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Publication number: 20190139952
    Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 9, 2019
    Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Publication number: 20190120875
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Applicant: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10184956
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 22, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10119995
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 6, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Publication number: 20180267084
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10002839
    Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 19, 2018
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Publication number: 20180061788
    Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 1, 2018
    Applicant: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Publication number: 20180061790
    Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 1, 2018
    Applicant: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Publication number: 20180061789
    Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 1, 2018
    Applicant: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung