Patents by Inventor Wen-Yuan Chang
Wen-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180061672Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.Type: ApplicationFiled: June 29, 2017Publication date: March 1, 2018Applicant: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
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Patent number: 9905519Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.Type: GrantFiled: June 29, 2017Date of Patent: February 27, 2018Assignee: VIA Alliance Semiconductor Co., Ltd.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
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Patent number: 9788425Abstract: An electronic package assembly is provided. The electronic package assembly includes a package substrate having a first surface and a second surface opposite thereto. A plurality of conductive pads is disposed on the first surface. A chip is mounted onto the first surface of the package substrate. A circuit board is mounted onto the second surface of the package substrate, and includes an electrical connector. A plurality of electrical contact components is electrically connected to the electrical connector and is in contact with the plurality of conductive pads.Type: GrantFiled: December 3, 2015Date of Patent: October 10, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Wen-Yuan Chang, Kuo-Ying Tsai
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Publication number: 20160302306Abstract: An electronic package assembly is provided. The electronic package assembly includes a package substrate having a first surface and a second surface opposite thereto. A plurality of conductive pads is disposed on the first surface. A chip is mounted onto the first surface of the package substrate. A circuit board is mounted onto the second surface of the package substrate, and includes an electrical connector. A plurality of electrical contact components is electrically connected to the electrical connector and is in contact with the plurality of conductive pads.Type: ApplicationFiled: December 3, 2015Publication date: October 13, 2016Inventors: Nai-Shung CHANG, Wen-Yuan CHANG, Kuo-Ying TSAI
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Patent number: 9425066Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.Type: GrantFiled: November 26, 2012Date of Patent: August 23, 2016Assignee: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang
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Patent number: 9418964Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.Type: GrantFiled: March 26, 2012Date of Patent: August 16, 2016Assignee: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Wei-Chih Lai
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Patent number: 9324580Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.Type: GrantFiled: July 2, 2015Date of Patent: April 26, 2016Assignee: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang
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Publication number: 20150303074Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.Type: ApplicationFiled: July 2, 2015Publication date: October 22, 2015Inventors: Chen-Yueh Kung, Wen-Yuan Chang
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Publication number: 20150123690Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.Type: ApplicationFiled: January 8, 2014Publication date: May 7, 2015Applicant: VIA Technologies, Inc.Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
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Patent number: 8796848Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.Type: GrantFiled: January 11, 2011Date of Patent: August 5, 2014Assignee: Via Technologies, Inc.Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Yeh-Chi Hsu
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Patent number: 8698325Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.Type: GrantFiled: March 17, 2011Date of Patent: April 15, 2014Assignee: VIA Technologies, Inc.Inventors: Wen-Yuan Chang, Yu-Kai Chen, Yeh-Chi Hsu, Ying-Ni Lee, Wei-Chih Lai
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Publication number: 20140077357Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.Type: ApplicationFiled: November 26, 2012Publication date: March 20, 2014Applicant: VIA TECHNOLOGIES, INC.Inventors: Chen-Yueh Kung, Wen-Yuan Chang
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Patent number: 8602207Abstract: A conveyor-belt linking apparatus utilizes a movable frame slidably disposed on a predetermined supporting surface, a plurality of pivot shafts disposed on the movable frame to support a load object, at least one primary driving element disposed between the movable frame and the predetermined supporting surface to drive the movable frame to reciprocally and slidably move along a predetermined direction, and an engaging driving assembly including a side driving element capable of being outwardly input with a power and a transmission assembly. The transmission assembly capable of synchronically sliding with the movable frame is connected to the side driving element for transmitting the power of the side driving element to rotate each of the pivot shafts. With the movable frame capable of sliding between two conveying positions, the defects of inclination, vibration and sway of the load object resulted from a large clearance between the pivot shafts can be decreased.Type: GrantFiled: August 17, 2011Date of Patent: December 10, 2013Inventor: Wen Yuan Chang
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Patent number: 8508024Abstract: A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.Type: GrantFiled: November 16, 2010Date of Patent: August 13, 2013Assignee: VIA Technologies, IncInventor: Wen-Yuan Chang
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Publication number: 20130175681Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.Type: ApplicationFiled: March 26, 2012Publication date: July 11, 2013Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Wei-Chih Lai
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Publication number: 20130055764Abstract: A crystal growth furnace is disclosed herein and includes a top cover, a body and a bottom portion. The top cover is configured to be moved by a top cover shifting mechanism. The body is configured to be moved vertically by a body shifting mechanism. The bottom portion is configured to be moved from the bottom of the crystal growth furnace by a bottom portion shifting mechanism and used to carry a crucible. When the top cover, the body and the bottom portion are connected together to be the crystal growth furnace, a silicon material disposed within the crucible is grown to be an ingot.Type: ApplicationFiled: September 6, 2011Publication date: March 7, 2013Applicant: REAL GREEN MATERIAL TECHNOLOGY CORP.Inventor: Wen-Yuan Chang
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Publication number: 20130043108Abstract: A conveyor-belt cooling apparatus includes primary frames, bearings respectively disposed on the primary frames, pivot shafts, inner tubes and at least one refrigerant pipeline assembly. Two ends of the pivot shaft combined in the corresponding bearings are disposed on the primary frames. The inner tubes are penetrated through and disposed in each of the pivot shafts so that the inner tubes and the pivot shaft form a relative sliding therebetween. The refrigerant pipeline assembly is assembled by refrigerant conduits and one refrigerant engaging pipe. The inner tubes are connected by the refrigerant engaging pipe therebetween to form the refrigerant engaging pipe with a serial connection status, and the refrigerant conduits are engaged to the serially connected inner tubes, absorbing heat flux of the pivot shafts by the inner tubes and guiding a refrigerant in and out of the inner tubes by the refrigerant conduits to form a heat-dissipative circulation.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Inventor: WEN YUAN CHANG
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Publication number: 20130043109Abstract: A conveyor-belt linking apparatus utilizes a movable frame slidably disposed on a predetermined supporting surface, a plurality of pivot shafts disposed on the movable frame to support a load object, at least one primary driving element disposed between the movable frame and the predetermined supporting surface to drive the movable frame to reciprocally and slidably move along a predetermined direction, and an engaging driving assembly including a side driving element capable of being outwardly input with a power and a transmission assembly. The transmission assembly capable of synchronically sliding with the movable frame is connected to the side driving element for transmitting the power of the side driving element to rotate each of the pivot shafts. With the movable frame capable of sliding between two conveying positions, the defects of inclination, vibration and sway of the load object resulted from a large clearance between the pivot shafts can be decreased.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Inventor: WEN YUAN CHANG
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Publication number: 20130020745Abstract: An automatic continuous feeding device of a metallurgical furnace includes an outer barrel and a plurality of inner barrels. The outer barrel includes an accommodation space having an out-feed channel communicated to a reduction furnace. An out-feed gate is disposed on the out-feed channel of the outer barrel. The inner barrels utilized to receive a material are disposed in the accommodation space of the outer barrel. Each of the inner barrels includes an in-feed opening and an out-feed opening, wherein the in-feed opening passing through the outer barrel to communicate to an exterior is enclosed by an openable cover enclosing mechanism, and an inner-barrel lower cover is disposed on each of the out-feed openings. The accommodation space of the outer barrel can be kept at an environmental temperature and pressure equal to that of the reduction furnace, to perform multiple feeding operations in an environment with constant temperature and pressure.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Inventor: WEN YUAN CHANG
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Publication number: 20130009349Abstract: A separation type metallurgical reduction method and an apparatus thereof. The separation type metallurgical reduction apparatus includes a reduction furnace and a multistage cooling device. By means of the separation type metallurgical reduction apparatus, the metallurgical reduction/smelting process and the cooling process are separately performed in different spaces at the same time to improve the operation of the conventional metallurgical reduction furnace within which the smelting process and the cooling process are totally limitedly performed. Accordingly, the shortcomings of too long waiting time, waste of great amount of energy and low yield rate that exist in the conventional metallurgical reduction furnace can be eliminated.Type: ApplicationFiled: July 5, 2011Publication date: January 10, 2013Inventor: WEN YUAN CHANG