Abstract: A package box module for packaging an object is disclosed, which includes a package box having a sidewall and plural first coupling structures disposed on the sidewall, and a common cushion disposed between the object and the sidewall. The common cushion includes plural second coupling structures and plural flexible structures disposed between the second coupling structures. The common cushion can be enlarged by extending the flexible structures, so that the first coupling structures couple to the second coupling structures, thus a gap between the object and the package box is filled by the common cushion.

Abstract: A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.

Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.

Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.

Abstract: A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.

Abstract: An electronic apparatus including a main board, an input/output (I/O) board, and a flexible printed circuit (FPC) is provided. The main board includes a first carrier, a central processing unit (CPU), a north bridge unit, a south bridge unit, a basic input/output system (BIOS), a memory module, a clock generator, a graphic unit, and at least one power management. The CPU, the north bridge unit, the south bridge unit, the BIOS, the memory module, the clock generator, the graphic unit, and the power management are disposed on the first carrier. The I/O board includes a second carrier an I/O module and an I/O connector. The I/O module and the I/O connector are disposed on the second carrier. The FPC connects the first carrier and the second carrier.

Abstract: A package structure for packaging a panel module. The panel module comprises at least a gap. The package structure comprises a base and a cover. The base comprises a first loading surface for loading the panel module and at least one first engaging portion corresponding to the gap. The cover comprises a first covering surface and a second engaging portion corresponding to the first engaging portion. The first engaging portion and the second engaging portion connect the first loading surface and the first covering surface.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

Abstract: A method of operating an optical module/printer module system through a changer such that either the optical module or the printer module is driven. A first module and a second module is defined such that if the first module is an optical module, the second module is a printer module and if the first module is a printer module, the second module is an optical module. The operating method includes the following steps. In step one, the changer engages with the first module and drives the first module. In step two, the changer rotates so that the changer detaches from the first module and engages with the second module. In step three, the changer drives the second module.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

Abstract: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape and exposing bonding pads of the chip on the active surface respectively. Conductive material is deposited into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively. A multi-layered interconnection structure is formed on the tape on the opposite of the chip, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

Abstract: A method of operating an optical module/printer module system through a changer such that either the optical module or the printer module is driven. A first module and a second module is defined such that if the first module is an optical module, the second module is a printer module and if the first module is a printer module, the second module is an optical module. The operating method includes the following steps. In step one, the changer engages with the first module and drives the first module. In step two, the changer rotates so that the changer detaches from the first module and engages with the second module. In step three, the changer drives the second module.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.

Abstract: A carrier device for a contact image sense optical scanner. The carrier device incorporates a pair of magnets with identical poles facing each other or a fluid filled sealed chamber for exerting an equal pressure on a scanning module within the scanner and maintaining close contact with a document platform throughout a scanning operation.

Abstract: A package structure for packaging a panel module. The panel module comprises at least a gap. The package structure comprises a base and a cover. The base comprises a first loading surface for loading the panel module and at least one first engaging portion corresponding to the gap. The cover comprises a first covering surface and a second engaging portion corresponding to the first engaging portion. The first engaging portion and the second engaging portion connect the first loading surface and the first covering surface.

Abstract: The present invention is about an apparatus for scanning an object. The apparatus comprises an image capture module having a lens and a sensors array for capturing light after scanning the object. There are light sources comprising a visible light source and an infrared light source. Next, a key module of the present invention is a first translation module connected with the lens and the sensors array. The first translation module is-used for changing a first location of the lens and a second location of the sensors array according to using different the light sources so as to improve some optical characteristics, such as aberration resulting from different wavelengths of light sources. A power module connects with the first translation module and the light sources for supporting energy to the first translation module and the light sources. Moreover, a second translation module connects with the light sources and the image capture module, and the second translation driven by the power module.