Abstract: Provided are a gravure coating device for preparing a large-width ultrathin metal lithium strip and the preparation method, relating to the technical field of preparation of metal lithium materials.

Abstract: A formulation of conjugates of tubulysin analogs with a cell-binding molecule having a structure represented by Formula (I), wherein T, L, m, n, ----, R1, R2, R3, R4, R1, R6, R7, R1, R9, R10, R11, R12, and R13 are as defined herein, can be used for targeted treatment of cancer, autoimmune disease, and infectious disease.

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.

Abstract: A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer.

Abstract: A floating solar system, comprising a floating base having, a buoyance and a lower base frame coupled to the buoyance, a center frame coupled to the lower base frame, an anchor coupled to the lower base frame, a plurality of solar panels affixed to the lower base frame and the center frame to provide electrical power, a lightning rod coupled to the center frame and a lightning rod cap coupled to the lightning rod.

Abstract: A train speed estimation device and method are disclosed. Vibration in a natural frequency band experienced by a train as it advances is sampled by means of first and second sensors at the same sampling frequency, to obtain a first set and a second set of sampling signals respectively; a first set and a second set of vibration signals are obtained on the basis of the first set and second set of sampling signals respectively, and the first set and second set of vibration signals are subjected to cross-correlation analysis, to obtain a target sampling difference; and a train speed is calculated on the basis of the target sampling difference. The train speed estimation device and method according to the present disclosure can precisely monitor the real-time train speed without relying on any speed sensor or GNSS.

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.

Abstract: The system comprises an electrode treatment unit; a temperature control treatment device (20a) connected in series to the electrode treatment unit, the temperature control treatment device (20a) comprising a temperature control vacuum treatment device (201) or a temperature control inert treatment device (202); and a lift-off unit connected in series to the temperature control treatment device (20a). Or the system comprises an atmosphere box (20b), the interior of the atmosphere box (20b) being vacuum, or an inert atmosphere and/or a protective atmosphere; and the electrode treatment unit provided inside the atmosphere box (20b), the temperature control box (9) connected in series to the electrode treatment unit, and the lift-off unit connected in series to the temperature control box (9). The electrode treatment unit comprises a first metal source unwinding shaft (1); a metal electrode unwinding shaft (2) to be supplemented and a compression roller device.

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

Abstract: A semiconductor device is provided, which includes a substrate, an active region, source and drain regions, first and second gate structures, and a contact structure. The active region is arranged over the substrate and the source and drain regions are arranged in the active region. The first and second gate structures abut upon the active region. The first gate structure is arranged between the source and drain regions and the second gate structure is arranged between the first gate structure and the drain region. The contact structure is arranged over the active region electrically coupling the first gate structure.

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

Abstract: A conjugation of a cytotoxic drug to a cell-binding molecule with a bis-linker (dual-linker) as shown in Formula (I). Bis-linkage methods of making a conjugate of a cytotoxic drug/molecule to a cell-binding agent in a specific manner are also described, as well as application of the conjugates for the treatment of a cancer, or an autoimmune disease, or an infectious disease. wherein “” is an optional bond; X, Y, Z1, and Z2 are a functional group; m1 and n are a integer; L1 and L2 are a linker.

Abstract: A UE may be configured to communicate using one of analog beamforming or hybrid beamforming. The UE may receive a set of beamformed signals from a base station. The UE may determine a set of angular spread values associated with a set of clusters in a channel between the base station and the UE based on the set of beamformed signals received from the base station. The UE may transmit the set of angular spread values to the base station. The UE may receive, from the base station based on the set of angular spread values, a set of transmission ranks associated with at least one cluster of the set of clusters. The UE may communicate at least one data stream with the base station across the at least one cluster using the set of transmission ranks associated with the at least one cluster of the set of clusters.

Abstract: The present invention discloses a bead wire wrapper device and a wrapper method.

Abstract: A conjugation of a cytotoxic drug to a cell-binding molecule with a bis-linker (dual-linker) as shown in Formula (I). Bis-linkage methods of making a conjugate of a cytotoxic drug/molecule to a cell-binding agent in a specific manner are also described, as well as application of the conjugates for the treatment of a cancer, or an autoimmune disease, or an infectious disease. wherein “” is an optional bond; X, Y, Z1, and Z2 are a functional group; m1 and n are a integer; L1 and L2 are a linker.