Abstract: The present invention relates to novel linkers containing a 2,3-disubstituted succinic group, or 2-monosubstituted, or 2,3-disubstituted fumaric or maleic (trans (E)- or cis (Z)-butenedioic), or acetylenedicarboxyl group for conjugation of a cytotoxic agent, and/or one or more different functional molecules per linker to a cell-binding molecule, through bridge linking pairs of thiols on the cell-binding molecule specifically. The invention also relates to methods of making such linkers, and of using such linkers in making homogeneous conjugates, as well as of application of the conjugates in treatment of cancers, infections and autoimmune disorders.

Abstract: A backlight source module and a display device are provided. The backlight source module includes a back plate structure and a rubber member. The back plate structure includes a bottom plate, and a first side plate and a second side plate respectively connected with the bottom plate, and the first side plate and the second side plate oppose each other. A light-emitting portion, a light-guiding component and the rubber member are sequentially disposed on the bottom plate along a first direction pointing from the first side plate to the second side plate. The rubber member is only disposed at the second side plate.

Abstract: Provided are an asynchronous heating and calendering device, a large wide ultra-thin lithium metal foil, and preparation method and use thereof, wherein the asynchronous heating and calendering device comprises: a pulling-substrate unwinding unit (E) for unwinding a pulling-substrate (P); a lithium strip unwinding unit (D) for unwinding a lithium strip (S); an asynchronous heating and calendering unit (H) which comprises: a first calendering roller (B), a second calendering roller (A) and a heating box (C), wherein the heating box (C) is used to heat the first calendering roller (B), the first calendering roller (B) heats the pulling-substrate (P), and the first calendering roller (B) and the second calendering roller (A) have parallel axes and are arranged opposite to each other, so that the pulling-substrate (P) and the lithium strip (S) are combined into a composite strip (Z); and a winding unit (G) for winding the composite strip (Z).

Abstract: Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.

Abstract: The present invention relates to linkers having a group of propiolyl, substituted acryl (acryloyl), or disubstituted propanoyl, and using such linkers for the conjugation of compounds, in particular, cytotoxic agents to a cell-binding molecule.

Abstract: The present invention relates to linkers having a group of propiolyl, substituted acryl (acryloyl), or disubstituted propanoyl, and using such linkers for the conjugation of compounds, in particular, cytotoxic agents to a cell-binding molecule.

Abstract: The present invention relates to linkers having a group of propiolyl, substituted acryl (acryloyl), or disubstituted propanoyl, and using such linkers for the conjugation of compounds, in particular, cytotoxic agents to a cell-binding molecule.

Abstract: The present invention relates to linkers having a group of propiolyl, substituted acryl (acryloyl), or disubstituted propanoyl, and using such linkers for the conjugation of compounds, in particular, cytotoxic agents to a cell-binding molecule.

Abstract: Provided are a gravure coating device for preparing a large-width ultrathin metal lithium strip and the preparation method, relating to the technical field of preparation of metal lithium materials.

Abstract: A formulation of conjugates of tubulysin analogs with a cell-binding molecule having a structure represented by Formula (I), wherein T, L, m, n, ----, R1, R2, R3, R4, R1, R6, R7, R1, R9, R10, R11, R12, and R13 are as defined herein, can be used for targeted treatment of cancer, autoimmune disease, and infectious disease.

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.

Abstract: A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer.

Abstract: A floating solar system, comprising a floating base having, a buoyance and a lower base frame coupled to the buoyance, a center frame coupled to the lower base frame, an anchor coupled to the lower base frame, a plurality of solar panels affixed to the lower base frame and the center frame to provide electrical power, a lightning rod coupled to the center frame and a lightning rod cap coupled to the lightning rod.

Abstract: A train speed estimation device and method are disclosed. Vibration in a natural frequency band experienced by a train as it advances is sampled by means of first and second sensors at the same sampling frequency, to obtain a first set and a second set of sampling signals respectively; a first set and a second set of vibration signals are obtained on the basis of the first set and second set of sampling signals respectively, and the first set and second set of vibration signals are subjected to cross-correlation analysis, to obtain a target sampling difference; and a train speed is calculated on the basis of the target sampling difference. The train speed estimation device and method according to the present disclosure can precisely monitor the real-time train speed without relying on any speed sensor or GNSS.

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.