Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A method and system for controlling the output power from a renewable energy installation (10) to a utility grid (56) having a predetermined bound for a variation in output power per unit of time is provided. The method and system includes constraining an output signal of a controller (76) to an upper and/or lower limit via a limiter (78), wherein the upper and/or lower limit comprises a predetermined upper and/or lower bound for a variation in output power per unit of time. The constrained output signal is then applied to the plurality of electricity generators (12, 14, 16) to limit the variation in output power per unit of time according to the predetermined bound.

Abstract: A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

Abstract: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.

Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.

Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

Abstract: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.

Abstract: A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.

Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

Abstract: Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

Abstract: Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

Abstract: Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.

Abstract: A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.