Patents by Inventor William J. Lambert

William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210304952
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Patent number: 11112841
    Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Divya Mani, William J. Lambert, Shawna Liff, Sergio A. Chan Arguedas, Robert L. Sankman
  • Publication number: 20210233867
    Abstract: Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 29, 2021
    Inventors: Bassam ZIADEH, Joseph VAN NAUSDLE, Zhou YANG, William J. LAMBERT, Mitul MODI
  • Patent number: 10998120
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Publication number: 20210125944
    Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: William J. LAMBERT, Sri Chaitra Jyotsna CHAVALI
  • Publication number: 20210036618
    Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.
    Type: Application
    Filed: September 28, 2017
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: WILLIAM J. Lambert, Kaladhar Radhakrishnan, Beomseok Choi, Krishna Bharath, Michael J. Hill
  • Patent number: 10868366
    Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, William J. Lambert
  • Publication number: 20200303822
    Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.
    Type: Application
    Filed: September 29, 2017
    Publication date: September 24, 2020
    Inventors: Jimin YAO, Shawna M. LIFF, William J. LAMBERT, Zhichao ZHANG, Robert L. SANKMAN, Sri Chaitra J. CHAVALI
  • Patent number: 10741536
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
  • Publication number: 20200203470
    Abstract: A conductive metal pillar is disposed within a composite material used as a die overflow material to form inductor on a module substrate. In situ fabrication of inductors on a module substrate enable customized selection of an inductance value, thus enabling inductors (and other similar peripheral devices) to be placed on a module substrate rather than on a motherboard. Furthermore, these in situ fabricated peripheral devices may also be used to remove excess heat produced by a die because the magnetic particles of the composite material are also thermally conductive. Furthermore, electrically conductive elements of the peripheral devices can be placed in contact with the die and/or integrated heat spreader.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Kedar Dhane, Malavarayan Sankarasubramanian, Yongki Min, William J. Lambert
  • Patent number: 10658765
    Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
  • Publication number: 20200076046
    Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Omkar KARHADE, William J. LAMBERT, Xiaoqian LI, Sidharth DALMIA
  • Publication number: 20200066659
    Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Omkar Karhade, Martin Rodriguez, Gregorio R. Murtagian
  • Publication number: 20200036095
    Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.
    Type: Application
    Filed: January 4, 2017
    Publication date: January 30, 2020
    Inventors: Adel A. ELSHERBINI, Shawna M. LIFF, William J. LAMBERT
  • Publication number: 20200013693
    Abstract: An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventor: William J. Lambert
  • Publication number: 20200006305
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Krishna Bharath, Beomseok Choi, Robert Sankman
  • Publication number: 20200006866
    Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
  • Publication number: 20190377392
    Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.
    Type: Application
    Filed: April 1, 2017
    Publication date: December 12, 2019
    Inventors: Divya MANI, William J. LAMBERT, Shawna LIFF, Sergio A. CHAN ARGUEDAS, Robert L. SANKMAN
  • Patent number: 10503227
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
  • Publication number: 20190279973
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material: a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadla, Clive R. Hendricks