Patents by Inventor William J. Lambert
William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250226583Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: ApplicationFiled: March 25, 2025Publication date: July 10, 2025Applicant: Intel CorporationInventors: Jimin Yao, Robert L. Sankman, Shawna M. Liff, Sri Chaitra Jyotsna Chavali, William J. Lambert, Zhichao Zhang
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Patent number: 12347782Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.Type: GrantFiled: September 15, 2021Date of Patent: July 1, 2025Assignee: Intel CorporationInventors: Sanka Ganesan, William J. Lambert, Bharat Prasad Penmecha, Xavier Francois Brun
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Publication number: 20250158269Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: ApplicationFiled: January 17, 2025Publication date: May 15, 2025Applicant: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 12288750Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.Type: GrantFiled: September 24, 2021Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: William J. Lambert, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini
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Publication number: 20250118698Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.Type: ApplicationFiled: December 19, 2024Publication date: April 10, 2025Applicant: Intel CorporationInventors: Xavier Francois Brun, Sanka Ganesan, Holly Sawyer, William J. Lambert, Timothy A. Gosselin, Yuting Wang
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Patent number: 12255382Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: GrantFiled: November 8, 2023Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 12242290Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.Type: GrantFiled: September 24, 2021Date of Patent: March 4, 2025Assignee: Intel CorporationInventors: Beomseok Choi, William J. Lambert, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini, Henning Braunisch, Stephen Morein, Aleksandar Aleksov, Feras Eid
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Publication number: 20250071885Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 12224252Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.Type: GrantFiled: September 23, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Krishna Bharath, William J. Lambert, Haifa Hariri, Siddharth Kulasekaran, Mathew Manusharow, Anne Augustine
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Publication number: 20250022814Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.Type: ApplicationFiled: September 26, 2024Publication date: January 16, 2025Inventors: William J. LAMBERT, Sri Chaitra Jyotsna CHAVALI
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Patent number: 12200855Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: GrantFiled: January 22, 2024Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 12170244Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.Type: GrantFiled: June 26, 2020Date of Patent: December 17, 2024Assignee: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Henning Braunisch, Beomseok Choi, William J. Lambert, Stephen Morein, Ahmed Abou-Alfotouh, Johanna Swan
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Patent number: 12154710Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.Type: GrantFiled: September 18, 2020Date of Patent: November 26, 2024Assignee: Intel CorporationInventors: Anuj Modi, Huong Do, William J. Lambert, Krishna Bharath, Harish Krishnamurthy
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Patent number: 12132015Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.Type: GrantFiled: October 28, 2019Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: William J. Lambert, Sri Chaitra Jyotsna Chavali
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Patent number: 12068684Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.Type: GrantFiled: September 23, 2020Date of Patent: August 20, 2024Assignee: Intel CorporationInventors: Krishna Bharath, Christopher Schaef, William J. Lambert, Kaladhar Radhakrishnan
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Publication number: 20240203978Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based clamp structure is above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.Type: ApplicationFiled: December 20, 2022Publication date: June 20, 2024Inventors: Samuel James BADER, Nachiket Venkappayya DESAI, Harish KRISHNAMURTHY, Han Wui THEN, William J. LAMBERT, Jingshu YU
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Patent number: 12002745Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.Type: GrantFiled: December 7, 2021Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
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Publication number: 20240164010Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 11937367Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: GrantFiled: July 3, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Publication number: 20240072419Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann