Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

Abstract: Apparatus and methods are provided for a wire based inductor component. In an example, an inductor apparatus can include a wire and a plurality of individual layers of magnetic material surrounding the wire.

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

Abstract: Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling capacitor coupled to the TSV's. A method including providing a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; coupling a decoupling capacitor to the backside of the die. An apparatus including a computing device including a package including a microprocessor including a device side and a backside with through silicon vias (TSV's) extending from the device side to the backside, and a decoupling capacitor coupled to the backside of the die; and a printed circuit board, wherein the package is coupled to the printed circuit board.