Patents by Inventor William J. Lambert
William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10868366Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.Type: GrantFiled: January 4, 2017Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, William J. Lambert
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Publication number: 20200303822Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: ApplicationFiled: September 29, 2017Publication date: September 24, 2020Inventors: Jimin YAO, Shawna M. LIFF, William J. LAMBERT, Zhichao ZHANG, Robert L. SANKMAN, Sri Chaitra J. CHAVALI
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Patent number: 10741536Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.Type: GrantFiled: May 30, 2019Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
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Publication number: 20200203470Abstract: A conductive metal pillar is disposed within a composite material used as a die overflow material to form inductor on a module substrate. In situ fabrication of inductors on a module substrate enable customized selection of an inductance value, thus enabling inductors (and other similar peripheral devices) to be placed on a module substrate rather than on a motherboard. Furthermore, these in situ fabricated peripheral devices may also be used to remove excess heat produced by a die because the magnetic particles of the composite material are also thermally conductive. Furthermore, electrically conductive elements of the peripheral devices can be placed in contact with the die and/or integrated heat spreader.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: INTEL CORPORATIONInventors: Kedar Dhane, Malavarayan Sankarasubramanian, Yongki Min, William J. Lambert
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Patent number: 10658765Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.Type: GrantFiled: June 28, 2018Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
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Publication number: 20200076046Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Omkar KARHADE, William J. LAMBERT, Xiaoqian LI, Sidharth DALMIA
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Publication number: 20200066659Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: Intel CorporationInventors: William J. Lambert, Omkar Karhade, Martin Rodriguez, Gregorio R. Murtagian
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Publication number: 20200036095Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.Type: ApplicationFiled: January 4, 2017Publication date: January 30, 2020Inventors: Adel A. ELSHERBINI, Shawna M. LIFF, William J. LAMBERT
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Publication number: 20200013693Abstract: An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 9, 2018Publication date: January 9, 2020Applicant: Intel CorporationInventor: William J. Lambert
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Publication number: 20200006866Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
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Publication number: 20200006305Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: Intel CorporationInventors: William J. Lambert, Krishna Bharath, Beomseok Choi, Robert Sankman
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Publication number: 20190377392Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.Type: ApplicationFiled: April 1, 2017Publication date: December 12, 2019Inventors: Divya MANI, William J. LAMBERT, Shawna LIFF, Sergio A. CHAN ARGUEDAS, Robert L. SANKMAN
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Patent number: 10503227Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.Type: GrantFiled: September 5, 2017Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
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Publication number: 20190279973Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material: a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.Type: ApplicationFiled: May 30, 2019Publication date: September 12, 2019Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadla, Clive R. Hendricks
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Patent number: 10340260Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.Type: GrantFiled: March 5, 2018Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
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Publication number: 20190051447Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
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Patent number: 10163557Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.Type: GrantFiled: December 17, 2015Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
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Patent number: 10157860Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.Type: GrantFiled: December 28, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Omkar G. Karhade, Kedar Dhane, Yongki Min, William J. Lambert
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Publication number: 20180332708Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.Type: ApplicationFiled: December 26, 2015Publication date: November 15, 2018Inventors: William J. LAMBERT, Mihir K. ROY, Mathew J. MANUSHAROW
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Publication number: 20180323708Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.Type: ApplicationFiled: December 22, 2015Publication date: November 8, 2018Inventors: William J. LAMBERT, Mathew MANUSHAROW