Patents by Inventor William J. Lambert

William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170092575
    Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
    Type: Application
    Filed: December 6, 2016
    Publication date: March 30, 2017
    Inventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert
  • Publication number: 20170092412
    Abstract: Embodiments of the invention include inductors integrated into a package substrate that have increased thicknesses due to the use of shaped vias, and methods of forming such packages. In an embodiment of the invention an inductor may be formed in a package substrate may include a first inductor line formed on the package substrate. In some embodiments, a shaped via may be formed over the first inductor line. Additional embodiments may include a dielectric layer that is formed over the package substrate, the first inductor line and around the shaped via. In one embodiment, a second inductor line may also be formed over the shaped via. Some embodiments of the invention may include an inductor that is a spiral inductor.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Mathew J. Manusharow, Yonggang Li, William J. Lambert, Krishna Bharath, Adel A. Elsherbini, Feras Eid, Aleksandar Aleksov, Henning Braunisch
  • Publication number: 20170092573
    Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Mathew J. MANUSHAROW, Daniel N. SOBIESKI, Mihir K. ROY, William J. LAMBERT
  • Publication number: 20170060205
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
    Type: Application
    Filed: August 26, 2015
    Publication date: March 2, 2017
    Inventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
  • Publication number: 20170012029
    Abstract: An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling capacitor coupled to the TSV's. A method including providing a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; coupling a decoupling capacitor to the backside of the die. An apparatus including a computing device including a package including a microprocessor including a device side and a backside with through silicon vias (TSV's) extending from the device side to the backside, and a decoupling capacitor coupled to the backside of the die; and a printed circuit board, wherein the package is coupled to the printed circuit board.
    Type: Application
    Filed: March 28, 2014
    Publication date: January 12, 2017
    Inventors: William J. LAMBERT, Robert L. SANKMAN, Tyler N. OSBORN, Charles A. GEALER
  • Publication number: 20160300824
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Patent number: 9397071
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20160043056
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Applicant: INTEL CORPORATION
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Patent number: 9230944
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: January 5, 2016
    Assignee: INTEL CORPORATION
    Inventors: William J. Lambert, Michael J. Hill, Kaladhar Radhakrishnan
  • Patent number: 9177831
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20150163904
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20150091182
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Patent number: 8243410
    Abstract: A transient voltage compensation system is provided. The transient voltage compensation system includes a processor and a first voltage regulator coupled to the processor, wherein the first voltage regulator is to deliver a load current to the processor at an output voltage. The transient voltage compensation system also includes a second voltage regulator coupled to the first voltage regulator, wherein the second voltage regulator is to regulate the output voltage in response to transient loads of the processor.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: August 14, 2012
    Assignee: Intel Corporation
    Inventors: Rajapandian Ayyanar, William J. Lambert, Shamala A. Chickamenahalli
  • Publication number: 20090279224
    Abstract: A transient voltage compensation system is provided. The transient voltage compensation system includes a processor and a first voltage regulator coupled to the processor, wherein the first voltage regulator is to deliver a load current to the processor at an output voltage. The transient voltage compensation system also includes a second voltage regulator coupled to the first voltage regulator, wherein the second voltage regulator is to regulate the output voltage in response to transient loads of the processor.
    Type: Application
    Filed: May 7, 2008
    Publication date: November 12, 2009
    Inventors: Rajapandian Ayyanar, William J. Lambert, Shamala A. Chickamenahalli
  • Patent number: 6828303
    Abstract: There are disclosed methods for the treatment of non-insulin dependent diabetes mellitus in a mammal comprising the prolonged administration of GLP-1 (7-37), and related peptides. Also disclosed are compositions to prolong the administration of the peptides.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: December 7, 2004
    Assignee: Scios, Inc.
    Inventors: Yesook Kim, William J. Lambert, Hong Qi, Robert A. Gelfand, Kieran F. Geoghegan, Dennis E. Danley
  • Patent number: 6643950
    Abstract: A cake resistance measuring system and method are used to measure the cake resistance of a freeze dried sample during or after processing, with the results of the measurement being used to improve that processing and/or subsequent freeze drying processes or formulations.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: November 11, 2003
    Assignee: Eisai Co., Ltd.
    Inventors: William J. Lambert, Zeren Wang
  • Publication number: 20030050237
    Abstract: There are disclosed methods for the treatment of non-insulin dependent diabetes mellitus in a mammal comprising the prolonged administration of GLP-1 (7-37), and related peptides. Also disclosed are compositions to prolong the administration of the peptides.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 13, 2003
    Applicant: Scios Inc.
    Inventors: Yesook Kim, William J. Lambert, Hong Qi, Robert A. Gelfand, Kieran F. Geoghegan, Dennis E. Danley
  • Publication number: 20020121099
    Abstract: A cake resistance measuring system and method are used to measure the cake resistance of a freeze dried sample during or after processing, with the results of the measurement being used to improve that processing and/or subsequent freeze drying processes or formulations.
    Type: Application
    Filed: December 4, 2001
    Publication date: September 5, 2002
    Inventors: William J. Lambert, Zeren Wang
  • Patent number: 6284727
    Abstract: There are disclosed methods for the treatment of non-insulin dependent diabetes mellitus in a mammal comprising the prolonged administration of GLP-1 (7-37), and related peptides. Also disclosed are compositions to prolong the administration of the peptides.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 4, 2001
    Assignee: Scios, Inc.
    Inventors: Yesook Kim, William J. Lambert, Hong Qi, Robert A Gelfand, Kieran F. Geoghegan, Dennis E. Danley
  • Patent number: 4488224
    Abstract: A control system is described for controlling the flow of multi-format, multi-bit macroinstructions for loading data into registers. The control system is adapted to: (A) control microprogram flow of instructions based on data within a floating point macroinstruction, (B) speed up macroinstruction flow as a function of data within various fields of the macroinstruction, and (C) speed up macroinstruction branches.
    Type: Grant
    Filed: August 10, 1982
    Date of Patent: December 11, 1984
    Assignee: IPL Systems, Inc.
    Inventors: Stephen J. Ippolito, Arthur L. Singer, William J. Lambert