Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor package may include a substrate having a first plurality of substrate bond pads and a second plurality of substrate bond pads, and a semiconductor die having a first plurality of die bond pads and a second plurality of die bond pads. Each die bond pad, included in the first plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the first plurality of substrate bond pads, using bump bonding, and each die bond pad, included in the second plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the second plurality of substrate bond pads, using wire bonding.

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

Abstract: Continuous time linear equalization devices are disclosed. A continuous time linear equalization device may include a first circuit including a first differential amplification element coupled to a first adjustable source degeneration element. The continuous time linear equalization device may also include a second circuit having an input coupled to an output of the first circuit and including a second differential amplification element coupled to a second adjustable source degeneration element. Systems are also disclosed.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: A delay locked loop circuit includes a duty detector configured to detect a duty cycle of a clock signal, and to determine whether to perform a coarse duty cycle correction based on the detected duty, and a delay locked loop core. The delay locked loop core is configured to selectively perform the coarse duty cycle correction for the clock signal according to the determination of the duty detector, perform a coarse lock for the clock signal during a first time period different from a second time period in which the coarse duty cycle correction is performed, and perform a fine duty cycle correction and a fine lock for the clock signal.

Abstract: A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.