Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.

Abstract: A delay locked loop circuit includes a duty detector configured to detect a duty cycle of a clock signal, and to determine whether to perform a coarse duty cycle correction based on the detected duty, and a delay locked loop core. The delay locked loop core is configured to selectively perform the coarse duty cycle correction for the clock signal according to the determination of the duty detector, perform a coarse lock for the clock signal during a first time period different from a second time period in which the coarse duty cycle correction is performed, and perform a fine duty cycle correction and a fine lock for the clock signal.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to a first surface of the interposer, and a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to a second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view may be provided.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Abstract: A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced apart from the first conductive pattern; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including: a third conductive pattern; a fourth conductive pattern spaced apart from the third conductive pattern; a first through-substrate via (TSV) penetrating the second semiconductor die and electrically connecting the first conductive pattern with the third conductive pattern; and a second TSV penetrating the second semiconductor die and electrically connecting the second conductive pattern with the fourth conductive pattern, and a first conductive connection pattern included in the first semiconductor die and electrically connecting a first end of the first conductive pattern with a first end of the second conductive pattern, or included in the second semiconductor die and electrically connecting a first end of

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal.

Abstract: In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal.

Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal.

Abstract: In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal.

Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

Abstract: A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

Abstract: A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.