Abstract: A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.

Abstract: A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.

Abstract: A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.

Abstract: A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

Abstract: A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

Abstract: A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

Abstract: A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.

Abstract: A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

Abstract: A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.

Abstract: A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.

Abstract: A duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal.

Abstract: A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.

Abstract: A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.

Abstract: A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

Abstract: A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.

Abstract: A phase synchronization apparatus includes an oscillator gain setting member configured to discriminate a frequency by sequentially delaying input clock signal after dividing the input clock signal at a predetermined division ratio and to generate an oscillator gain setting signal by using discriminated frequency information, and a phase locked loop (PLL) circuit configured to oscillates output clock signal having a frequency corresponding to the oscillator gain setting signal in response to the input clock signal.

Abstract: A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.

Abstract: A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.

Abstract: A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a complementary phase multiplexing, and a cascade delay line. This device performs an operation by selecting any one of an external clock signal (CLK) and an inverted external clock signal (CLKB) using a multiplexing portion 200, aligning the selected clock signal at a rising edge of the external clock signal (CLK) through a first single coarse delay line 212, a first dual coarse delay line 222, and a first fine delay unit 223 according to the phase comparison with a feedback clock signal (FBCLK) through a delay model portion 250, then receiving a clock signal through the first single coarse delay line 212 to the second single coarse delay line 214 to align the rising edges of the rising clock signal (RCLK) and the falling clock signal (FCLK).

Abstract: A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.