Patents by Inventor Won-Joo Yun

Won-Joo Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090174447
    Abstract: A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.
    Type: Application
    Filed: July 18, 2008
    Publication date: July 9, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Hyun Woo Lee, Won Joo Yun
  • Patent number: 7557627
    Abstract: A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: July 7, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Woo Lee, Won-Joo Yun
  • Publication number: 20090146709
    Abstract: A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.
    Type: Application
    Filed: July 14, 2008
    Publication date: June 11, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Hyun Woo Lee, Won Joo Yun
  • Publication number: 20090146708
    Abstract: A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output
    Type: Application
    Filed: July 11, 2008
    Publication date: June 11, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Won Joo Yun, Hyun Woo Lee
  • Patent number: 7535270
    Abstract: A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 19, 2009
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Hyun-Woo Lee, Won-Joo Yun
  • Publication number: 20090121784
    Abstract: A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
    Type: Application
    Filed: July 17, 2008
    Publication date: May 14, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Hyun-Woo Lee, Won-Joo Yun, Dong-Suk Shin
  • Publication number: 20090058483
    Abstract: A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Dong-Suk Shin, Hyun-Woo Lee, Won-Joo Yun
  • Publication number: 20090003101
    Abstract: An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
    Type: Application
    Filed: January 14, 2008
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Won-Joo Yun, Hyun Woo Lee, Dong-Suk Shin
  • Publication number: 20090002039
    Abstract: A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Won Joo Yun, Hyun Woo Lee, Dong Suk Shin
  • Publication number: 20080252350
    Abstract: A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 16, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dong Suk Shin, Hyun Woo Lee, Won Joo Yun
  • Publication number: 20080252349
    Abstract: A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.
    Type: Application
    Filed: December 18, 2007
    Publication date: October 16, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Won Joo Yun, Hyun Woo Lee, Dong Suk Shin
  • Publication number: 20080174350
    Abstract: A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
    Type: Application
    Filed: July 16, 2007
    Publication date: July 24, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Dong Suk Shin, Hyun Woo Lee, Won Joo Yun
  • Publication number: 20080164922
    Abstract: A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.
    Type: Application
    Filed: July 20, 2007
    Publication date: July 10, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Won-Joo Yun, Hyun-Woo Lee
  • Publication number: 20080111600
    Abstract: An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.
    Type: Application
    Filed: July 5, 2007
    Publication date: May 15, 2008
    Applicant: Hynx Semiconductor Inc.
    Inventors: Won Joo Yun, Hyun Woo Lee, Nak Kyu Park
  • Publication number: 20080079470
    Abstract: A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Inventors: Won-Joo Yun, Hyun-Woo Lee
  • Publication number: 20080062809
    Abstract: A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.
    Type: Application
    Filed: March 8, 2007
    Publication date: March 13, 2008
    Inventors: Hyun-Woo Lee, Won-Joo Yun
  • Publication number: 20080054964
    Abstract: A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
    Type: Application
    Filed: June 29, 2007
    Publication date: March 6, 2008
    Inventors: Hyun-Woo Lee, Won-Joo Yun
  • Publication number: 20080001642
    Abstract: A delay-locked loop apparatus includes at least a rising-clock delay-locked circuit, a falling-clock delay-locked circuit, and a duty cycle compensation circuit. The rising-clock delay-locked circuit detects the phase difference between a first clock inputted as a reference clock and a second clock obtained by replica-delaying the first clock, and then delay-locks the first clock and outputs a rising clock. The falling-clock delay-locked circuit detects the phase difference between an inverted clock of the first clock and the rising clock after a delay locking operation with respect to the rising clock, delay-locks an inverted clock of the first clock and outputs a falling clock. The duty cycle compensation circuit compensates duty cycles of the delay-locked rising clock and falling clock, and the falling-clock delay-locked circuit includes a divider for separately dividing the inverted clock and the delay-locked rising clock.
    Type: Application
    Filed: March 8, 2007
    Publication date: January 3, 2008
    Inventors: Won Joo YUN, Hyun Woo LEE
  • Publication number: 20070262798
    Abstract: A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a complementary phase multiplexing, and a cascade delay line. This device performs an operation by selecting any one of an external clock signal (CLK) and an inverted external clock signal (CLKB) using a multiplexing portion 200, aligning the selected clock signal at a rising edge of the external clock signal (CLK) through a first single coarse delay line 212, a first dual coarse delay line 222, and a first fine delay unit 223 according to the phase comparison with a feedback clock signal (FBCLK) through a delay model portion 250, then receiving a clock signal through the first single coarse delay line 212 to the second single coarse delay line 214 to align the rising edges of the rising clock signal (RCLK) and the falling clock signal (FCLK).
    Type: Application
    Filed: March 8, 2007
    Publication date: November 15, 2007
    Inventors: Won Joo YUN, Hyun Woo LEE
  • Publication number: 20070200604
    Abstract: The present invention relates to a delay locked loop (DLL) apparatus. The DLL apparatus includes: a first delay means converting a reference clock into a rising clock; a second delay means converting the reference clock into a falling clock by delaying the reference clock; a replica delay unit replica-delaying the rising clock delayed by the first delay means; a first phase detection means comparing the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases; a control means synchronizing the rising edge of the rising clock with the rising edge of the reference clock in accordance with the first detection signal of the first phase detection means; and a second phase detection means comparing the phases of the rising clock synchronized by the control means and the synchronization clock to output a second detection signal corresponding to the compared phases.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 30, 2007
    Inventors: Won Joo YUN, Hyun Woo LEE