Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: To enable a user to cook both in a pressure state and in a non-pressure state inside the inner pot and thus improve cooking quality and ease of use, the present invention provides an electric cooker including a main body in which an inner pot for accommodating food is installed; a lid coupled to the main body to be opened or closed, in which a passthrough portion is formed; a pressure converter communicating with the passthrough portion, in which a selectively opened/closed state for discharging steam inside the inner pot is maintained; and a pressure-responsive actuators communicating with the passthrough portion and selectively opened/closed depending on a pressure level inside the inner pot in a pressure cooking mode.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: In a method for communication between hosts using a peripheral component interconnect express (PCIe) dedicated communication module, a PCIe dedicated communication module of a first host generates a first connection buffer for receiving a connection command from a second host, stands by a connection request from the second host, determines whether the first host is connectable to the second host in response to the connection request received from the second host, and, if it is determined that the first host is connectable to the second host, generates a first connection socket connected to the second host for the purpose of data communication. The PCIe dedicated communication module generates a first communication buffer to store data received from the second host, assigns the first communication buffer to the first connection socket, permits the connection between the first and second hosts, and stands by data communication with the second host.

Abstract: A heat radiation-thermoelectric fin includes a thermoelectric inorganic material on a heterogeneous laminate of graphene. The heterogeneous laminate may be tube-shaped or plate-shaped, and a metal conductor may be coupled to one or more of the heterogeneous laminate. A thermoelectric module may be formed to include the fin, and a thermoelectric apparatus may include a heat supplier connected to the thermoelectric module.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: A thermoelectric material includes a stack structure including alternately stacked first and second material layers. The first material layer may include a carbon nano-material. The second material layer may include a thermoelectric inorganic material. The first material layer may include a thermoelectric inorganic material in addition to the carbon nano-material. The carbon nano-material may include, for example, graphene. At least one of the first and second material layers may include a plurality of nanoparticles. The thermoelectric material may further include at least one conductor extending in an out-of-plane direction of the stack structure.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Abstract: Provided are a high-performance distributed storage apparatus and method. The high-performance distributed storage method includes receiving and storing file data by a chunk unit, outputting file data chunks stored in an input buffer and transmitting the file data chunks to data servers in parallel, additionally generating a new file storage requester to connect the new file storage requester to a new data server based on a data input speed of the input buffer and a data output speed at which data is output to the data server, re-setting a file data chunk output sequence for a plurality of file storage requesters including the new file storage requester, and applying a result of the re-setting to output and transmit the file data chunks stored in the input buffer to the data servers in parallel.

Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Abstract: Provided is a printed circuit board including a first conductive layer including a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion. A second conductive layer is disposed above the recessed portion of the first conductive layer. A core layer is disposed between the first conductive layer and the second conductive layer. An upper solder resist layer is disposed on the second conductive layer. The upper solder resist layer exposes at least a portion of the protruding portion. A lower solder resist layer is disposed below the first conductive layer.

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Abstract: Disclosed herein are a cloud service brokerage method and apparatus using a service image store. The cloud service brokerage apparatus includes a reception unit for receiving service requirements from each of users, a service image recommendation unit for recommending one or more candidate service images that satisfy the requirements among multiple service images stored in a service image store, a cloud server recommendation unit for recommending one or more candidate cloud servers that satisfy the requirements among multiple cloud servers, a registration unit for registering an optimal service image selected by the user from among the one or more candidate service images in an optimal cloud server selected by the user from among the one or more candidate cloud servers, and a transmission unit for transmitting results of a service implemented by executing the optimal service image on the optimal cloud server to the user.

Abstract: In a method for communication between hosts using a peripheral component interconnect express (PCIe) dedicated communication module, a PCIe dedicated communication module of a first host generates a first connection buffer for receiving a connection command from a second host, stands by a connection request from the second host, determines whether the first host is connectable to the second host in response to the connection request received from the second host, and, if it is determined that the first host is connectable to the second host, generates a first connection socket connected to the second host for the purpose of data communication. The PCIe dedicated communication module generates a first communication buffer to store data received from the second host, assigns the first communication buffer to the first connection socket, permits the connection between the first and second hosts, and stands by data communication with the second host.

Abstract: Provided is a printed circuit board including a first conductive layer including a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion. A second conductive layer is disposed above the recessed portion of the first conductive layer. A core layer is disposed between the first conductive layer and the second conductive layer. An upper solder resist layer is disposed on the second conductive layer. The upper solder resist layer exposes at least a portion of the protruding portion. A lower solder resist layer is disposed below the first conductive layer.

Abstract: Disclosed is a technology for controlling UI access to application software according to user's levels. The method for controlling UI access according to users' levels is characterized in providing a user with differentiated UI information according to user levels based on user-level-specific UI data in which UI information about functions to which access is allowed among functions provided by the application software is defined according to types of users.

Abstract: The present invention provides a method for preparing a BaX type zeolite granules comprising: adding a carbohydrate-based molding promoter to NaX type zeolite powder and thereto subsequently spraying and blending alumina sol and silica sol to form granules of the mixture; heating the formed granules to convert the alumina and silica component to aluminosilica so as to generate pores inside the formed granules; hydrothermally treating the resulted granules in a sodium hydroxide aqueous solution under the conditions for zeolite synthesis, thereby converting a portion of the aluminosilica to zeolite; and carrying out ion-exchanging by Ba ions. The present invention also provides BaX type zeolite granules which have excellent strength and can be suitably used as an adsorbent in simulated moving bed (SMB) application.