Patents by Inventor Won-Joon Choi

Won-Joon Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935926
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: March 19, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Patent number: 11675393
    Abstract: A display device according to an embodiment includes a display panel and a protection layer that is disposed on the display panel, wherein the protection layer includes: a first protection layer; a metal layer that overlaps the first protection layer and includes a hole; and an adhesive layer disposed between the first protection layer and the metal layer. The adhesive layer includes a first area disposed between the first protection layer and the metal layer, and a second area and a third area that are disposed in the hole, wherein a peeling strength of the second area and a peeling strength of the third area are different from each other.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ye Jin Kim, Seul-Gi Kim, Cheol Geun An, Eui Yun Jang, Won Joon Choi
  • Patent number: 11588026
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: February 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
  • Patent number: 11195988
    Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Yang-Kon Kim, Seung Mo Noh, Won-Joon Choi
  • Publication number: 20210297053
    Abstract: The present invention relates to a wave control apparatus using change of elastic modulus of thermoresponsive material, comprising: a wave modulation member having thermoresponsive material whose elastic modulus changes according to temperature variation, a wave source propagating wave through the wave modulation member, and a heating unit forming a wave modulation region by heating the wave modulation member, wherein the wave propagating through the wave modulation member from the wave source is configured to change wave characteristics when the wave passes through the wave modulation region heated by the heating unit.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 23, 2021
    Inventors: Won-Joon CHOI, Sang-Jun LEE, Haun-Min LEE
  • Publication number: 20210208636
    Abstract: A display device according to an embodiment includes a display panel and a protection layer that is disposed on the display panel, wherein the protection layer includes: a first protection layer; a metal layer that overlaps the first protection layer and includes a hole; and an adhesive layer disposed between the first protection layer and the metal layer. The adhesive layer includes a first area disposed between the first protection layer and the metal layer, and a second area and a third area that are disposed in the hole, wherein a peeling strength of the second area and a peeling strength of the third area are different from each other.
    Type: Application
    Filed: December 16, 2020
    Publication date: July 8, 2021
    Applicant: Samsung Display Co., LTD.
    Inventors: Ye Jin KIM, Seul-Gi KIM, Cheol Geun AN, Eui Yun JANG, Won Joon CHOI
  • Publication number: 20200388686
    Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.
    Type: Application
    Filed: January 13, 2020
    Publication date: December 10, 2020
    Inventors: Hyeng-Woo EOM, Jung-Myoung SHIM, Young-Ho YANG, Kwang-Wook LEE, Won-Joon CHOI
  • Patent number: 10818442
    Abstract: A method of fabricating a metal oxide film includes sequentially laminating a carbon film and a metal oxide film including nano-sized metal oxide nanoparticles on a porous fuel membrane to form a preliminary composite structure and reducing the metal oxide film to form a composite structure by combusting the porous fuel membrane while applying a voltage to the preliminary composite structure.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 27, 2020
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Won-joon Choi, Tae-han Yeo, Dong-joon Shin
  • Patent number: 10804043
    Abstract: A method of synthesizing multi-shell structure nanoparticles includes uniformly distributing core nanoparticles to a first porous fuel membrane, coating the core nanoparticles fixed to the first porous fuel membrane with a fuel, and combusting the fuel coated on the core nanoparticles and the first porous fuel membrane to coat a first carbon film on surfaces of the core nanoparticles.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 13, 2020
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Won-joon Choi, Tae-han Yeo, Dong-joon Shin
  • Patent number: 10777742
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10714499
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Patent number: 10615840
    Abstract: This disclosure provides techniques for managing antenna sharing on a multi-mode wireless device between coexisting cellular and WLAN modems operating on the same band. One of the modems can communicate a WLAN scanning parameter to another one of the modems, and the distribution of shared antennas between the cellular modem and the WLAN modem may be modified based at least in part on the communicated scanning parameter to accommodate a WLAN scan on channels in the shared band. The distribution of the shared antennas between the modems for the WLAN scan may additionally or alternatively be selected based at least in part on the source of a detected WLAN scanning trigger (e.g., whether the scan is triggered by an application of the wireless device or the WLAN modem of the wireless device).
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Heechoon Lee, Won-Joon Choi, Ning He
  • Publication number: 20200098984
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10586917
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 10, 2020
    Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Patent number: 10490741
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Publication number: 20190319045
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventors: Won Joon CHOI, Min Sung KO, Kyeong Bae KIM, Jong Gi KIM, Dong Sun SHEEN, Jung Myoung SHIM, Young Ho YANG, Hyeng Woo EOM, Kwang Wook LEE, Woo Jae CHUNG
  • Patent number: 10373973
    Abstract: The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Won Joon Choi, Min Sung Ko, Kyeong Bae Kim, Jong Gi Kim, Dong Sun Sheen, Jung Myoung Shim, Young Ho Yang, Hyeng Woo Eom, Kwang Wook Lee, Woo Jae Chung
  • Patent number: 10367137
    Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim
  • Publication number: 20190198262
    Abstract: A method of fabricating a metal oxide film includes sequentially laminating a carbon film and a metal oxide film including nano-sized metal oxide nanoparticles on a porous fuel membrane to form a preliminary composite structure and reducing the metal oxide film to form a composite structure by combusting the porous fuel membrane while applying a voltage to the preliminary composite structure.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 27, 2019
    Inventors: Won-joon CHOI, Tae-han YEO, Dong-joon SHIN
  • Publication number: 20190198261
    Abstract: A method of synthesizing multi-shell structure nanoparticles includes uniformly distributing core nanoparticles to a first porous fuel membrane, coating the core nanoparticles fixed to the first porous fuel membrane with a fuel, and combusting the fuel coated on the core nanoparticles and the first porous fuel membrane to coat a first carbon film on surfaces of the core nanoparticles.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 27, 2019
    Inventors: Won-joon CHOI, Tae-han YEO, Dong-joon SHIN