Abstract: A semiconductor package includes a first substrate, a first semiconductor die, a second semiconductor die, a second substrate, at least one first solder ball, at least one second solder ball, and at least one third solder ball. The first semiconductor die is disposed on the first substrate. The second semiconductor die is disposed on the first semiconductor die. The second substrate is disposed on the second semiconductor die. The first solder ball is vertically between the first substrate and the first semiconductor die. The second solder ball is vertically between the second substrate and the second semiconductor die. The third solder ball is vertically between the first substrate and the second substrate.

Abstract: The present disclosure provides a device die, a die assembly and an electronic system. The device die includes a package and a plurality of transfer pads disposed on a functional surface of the package. The transfer pads are divided into a plurality of segments electrically isolated from each other. In an adjacent pair of transfer pads, there is only one electrical connection between the transfer pads, comprising one segment in one transfer pad electrically connected to one segment in the other transfer pad. The die assembly includes a pair of device dies stacked in a stepped configuration. The electronic system includes a supporting member having at least one metallic layer, and a plurality of device dies disposed on the supporting member and mechanically and electrically coupled to the metallic layer by a plurality of conductive strings.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a plurality of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member includes a connection plate, a plurality of redistribution structures and a plurality of bumps. The connection plate is connected to the first die. The redistribution structures are connected to the second die. The bumps couple the connection plate to the redistribution structures. The bonding wires couple the interconnection member to the package substrate and the first die.

Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a plurality of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member includes a connection plate, a plurality of redistribution structures and a plurality of bumps. The connection plate is connected to the first die. The redistribution structures are connected to the second die. The bumps couple the connection plate to the redistribution structures. The bonding wires couple the interconnection member to the package substrate and the first die.

Abstract: The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad.

Abstract: A semiconductor device includes a substrate and a chip. The chip stacked on the substrate includes an active surface and at least one metal pad. The metal pad is disposed on the active surface and comprises a first pad portion and a second pad portion separated from the first pad portion to form an open circuit. The first pad portion includes a protrusion structure and the second pad portion includes a recess structure. Moreover, the protrusion structure of the first pad portion extends toward the recess structure of the second pad portion.

Abstract: An RDL structure including a first pad, a second pad, a third pad, a fourth pad, a first switch device, a second switch device, a third switch device, and a fourth switch device is provided. The first pad, the second pad, the third pad, and the fourth pad are separated from each other. The first switch device includes a first conductive layer and a second conductive layer separated from each other. The second switch device includes a third conductive layer and a fourth conductive layer separated from each other. The third switch device includes a fifth conductive layer and a sixth conductive layer separated from each other. The fourth switch device includes a seventh conductive layer and an eighth conductive layer separated from each other.

Abstract: An RDL structure including a first pad, a second pad, a third pad, a fourth pad, a first switch device, a second switch device, a third switch device, and a fourth switch device is provided. The first pad, the second pad, the third pad, and the fourth pad are separated from each other. The first switch device includes a first conductive layer and a second conductive layer separated from each other. The second switch device includes a third conductive layer and a fourth conductive layer separated from each other. The third switch device includes a fifth conductive layer and a sixth conductive layer separated from each other. The fourth switch device includes a seventh conductive layer and an eighth conductive layer separated from each other.

Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.

Abstract: A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.

Abstract: A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.

Abstract: The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad.

Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a number of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member is configured for coupling the first die and the second die and comprises a first connection plate, a second connection plate and a bump. The first connection plate is connected to the first die. The second connection plate is connected to the second die. The bump couples the first connection plate and the second connection plate. The bonding wires couple the interconnection member to the package substrate, the first die and the second die.

Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed thereon. The substrate includes first and second connection pads adjacent to a first edge of the semiconductor chip, and third and fourth connection pads adjacent to a second edge opposite to the first edge. The semiconductor chip includes fifth and sixth connection pads in a first region close to the first edge, and seventh and eighth connection pads in a second region close to the second edge. A first and a second comb-type conductive layer are further disposed over the first region, and respectively connected to the first and fifth connection pads, and the second and sixth connection pads via wirings. A third and a fourth comb-type conductive layer are further disposed over the second region, and respectively connected to the fourth and eighth connection pads, and the third and seventh connection pads via wirings.

Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

Abstract: A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved.

Abstract: A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip.