Abstract: An ambient-light-sensing hole structure package and a method of manufacturing the same are provided. The ambient-light-sensing hole structure package includes a transparent cover, a decorative layer, a porous structure layer, and an optical adhesive. The transparent cover has a surface. The decorative layer is disposed on the surface and the decorative layer has an opening that exposes a portion of the surface. The porous structure layer is disposed on one side of the decorative layer and the porous structure layer covers the portion of the surface. The porous structure layer includes a plurality of through holes, and the through holes overlap with the opening. The optical adhesive is interposed between the decorative layer and the porous structure layer.

Abstract: Modified release formulations, such as solid oral dosage forms comprising a core composition comprising Compound (I) and/or a pharmaceutically acceptable salt thereof; a sub-coating layer coating the core composition, said sub-coating layer comprising a polyvinyl alcohol and/or a hydroxypropyl methyl cellulose; and an enteric coating layer encapsulating the sub-coating layer and the core composition, said enteric coating layer comprising at least one polymer selected from an acrylic/methacrylic/ethacrylic acid homopolymer and copolymers thereof, a cellulose derivative, and a polyvinylpyrrolidone, and methods of administration of a Bruton's tyrosine kinase (BTK) inhibitor using said formulations.

Abstract: A touch panel capable of being simply manufactured includes a foldable substrate, a plurality of touch driving electrodes on the substrate, and a plurality of touch sensing electrodes on the substrate. The substrate includes two laminated layers achieved by folding. The touch driving electrodes are on one of the two laminated layers and the touch sensing electrodes are on the other of the two laminated layers. The touch driving electrodes and the touch sensing electrodes are formed by a same conductive layer on a surface of the substrate.

Abstract: A method of preparing perovskite quantum dots is provided. The method includes: adding an organic ligand into a first precursor solution prepared by a first halide and a second halide to form a second precursor solution, or adding the organic ligand into a first poor solvent to form a second poor solvent; spraying the first precursor solution into the second poor solvent or spraying the second precursor solution into the first poor solvent by a spraying method to obtain a mixed solution including first perovskite quantum dots and second quantum dots; centrifuging the mixed solution to obtain supernatant and precipitate; and obtaining the first perovskite quantum dots and the second perovskite quantum dots from the supernatant and the precipitate, respectively. The first perovskite quantum dots are different from the second perovskite quantum dots.

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

Abstract: A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.

Abstract: The touch panel includes a transparent substrate, a first touch-sensing electrode structure, a second touch-sensing electrode structure, and a patterned metal layer. The transparent substrate has a touch-sensing region and a peripheral region adjacent to at least one edge of the touch-sensing region. The first touch-sensing electrode structure is disposed on the touch-sensing region of the transparent substrate. The second touch-sensing electrode structure is positioned over the touch-sensing region and is configured to form at least one capacitor with the first touch-sensing electrode structure. The patterned metal layer has a plurality of first through holes located in the peripheral region and is extended on a level the same as the first touch-sensing electrode structure or the second touch-sensing electrode structure.

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

Abstract: Differing from conventional technology utilizing double-layer electron transport layer (ETL) to improving power conversion efficiency of perovskite solar cell, the present invention discloses a novel electron transport structure comprising an interfacial diploe moment enhancing layer, an electron transport layer and an interfacial layer. After applying this electron transport structure in a perovskite solar cell, it is found that an interfacial dipole moment formed between the electron transport layer of the electron transport structure and an active layer of the perovskite solar cell is amplified, so as to give rise to an enhanced driving force for the separation of photogenerated carriers and accelerating charge extraction.

Abstract: Compared to traditional ITO transparent substrate showing drawbacks of high sheet resistance, poor flexibility and high manufacturing cost, the present invention mainly discloses a transparent conductive film fabricated by sequentially forming a wetting layer and an ultra-thin metal layer onto a transparent substrate, wherein the transparent conductive film includes advantages of low sheet resistance, high transmittance, great flexibility, and low manufacturing cost. Moreover, a variety of experiment data have proved that, this novel transparent conductive film can not only be applied in the fabrication of some electro-optical devices such as organic solar cell and OLED, but also helpful to the enhancement of the fundamental and essential characteristics of the electro-optical devices.

Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.

Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

Abstract: A method of fabricating a perovskite solar cell includes forming a hole transport layer on a transparent electrically conductive substrate, and forming a perovskite layer on the hole transport layer via a two-stage vacuum evaporation process. Then, an electron transport layer and an electrode layer are formed in order. The two-stage vacuum evaporation process includes first vacuum evaporating a first material on the hole transport layer and then vacuum evaporating a second material on the first material so as to react the first material with the second material in situ and form the perovskite layer.

Abstract: A brick of an embodiment includes a concave first end, a convex second end, a first side, a second side, a top, and a bottom wherein the first end and the second end are complementary so that mortar filled the gaps between the first end of a brick and the second end of an adjacent brick may bind them together for a prolonged period of time. Further, holes are formed through top and bottom in another embodiment.

Abstract: The present disclosure provides a transparent conductive structure having metal mesh and including a transparent substrate, a first metal mesh structure, a first transparent insulating layer, a second metal mesh structure and a second transparent insulating layer. The transparent substrate has a top surface and a bottom surface opposite to the top surface. The first metal mesh structure is disposed on the top surface of the transparent substrate. The first transparent insulating layer surrounds the first metal mesh structure, and covers the top surface of the transparent substrate. The second metal mesh structure is disposed on the bottom surface of the transparent substrate. The second transparent insulating layer surrounds the second metal mesh structure, and covers the bottom surface of the transparent substrate.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A HDMI connector with anti-misinsertion structure includes a metallic case, a U-shaped plate, and a terminal base. The U-shaped plate is disposed on the upper surface of the metallic case, its front ends at which two push resilient plates and a block are disposed, respectively, its rear ends which extend to form two front arm potions connected to the push resilient plates and the block, and extends backward to form two rear arm portions and two base portions. The terminal base is installed thereon a terminal set. The anti-misinsertion structure is integrally formed with the metallic case to reduce manufacturing costs and boost linking-up and stopping strength of the anti-misinsertion structure, thereby preventing the non-HDMI plug from being inserted into the HDMI connector.

Abstract: A HDMI connector with anti-misinsertion structure includes a metallic case, a U-shaped plate, and a terminal base. The U-shaped plate is disposed on the upper surface of the metallic case, its front ends at which two push resilient plates and a block are disposed, respectively, its rear ends which extend to form two front arm potions connected to the push resilient plates and the block, and extends backward to form two rear arm portions and two base portions. The terminal base is installed thereon a terminal set. The anti-misinsertion structure is integrally formed with the metallic case to reduce manufacturing costs and boost linking-up and stopping strength of the anti-misinsertion structure, thereby preventing the non-HDMI plug from being inserted into the HDMI connector.