Abstract: A motor rotor, a self-starting synchronous reluctance motor including the same, and a compressor. The motor rotor includes a rotor core, and the rotor core includes a first rotor lamination, an end ring, and a second rotor lamination. Filling slots, rotor slots, and a shaft hole are formed in the first rotor lamination. The filling slots include first filling slots and two second filling slots. The second rotor lamination is arranged between the end ring and the first rotor lamination. Through slots are formed in the second rotor lamination at positions corresponding to the filling slots of the first rotor lamination respectively. A total cross-sectional area of first portions of the rotor slots on the first rotor lamination between an edge of an inner hole and an outer circle of the second rotor lamination is less than a total cross-sectional area of the rotor slots on the first rotor lamination.

Abstract: Techniques to form gate-all-around (GAA) and/or forksheet semiconductor devices that have varying semiconductor channel widths and varying numbers of semiconductor channel bodies (e.g., nanoribbons, nanosheets, nanowires). The techniques can be used in any number of transistor technologies, but are particularly useful in vertically stacked transistor configurations (e.g., stacked in a vertical z-direction from the substrate surface) and/or configurations that extend laterally in a horizontal x-or-y-direction). In an example, the n-channel device and the p-channel device may both be GAA or forksheet transistors each having any number of channel bodies extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Any number of adjacent devices may be patterned from a single fin to include varying channel body widths.

Abstract: Techniques to form semiconductor devices that include one or more fin isolation structures. Different ones of the fin isolation structures are configured with diverse materials, relative to other ones of the fin isolation structures, such that they cause or otherwise impose beneficial stress (e.g., tensile or compressive) on the adjacent semiconductor devices to improve performance. The semiconductor regions of devices may be interrupted with a fin isolation structure that includes dielectric material to electrically isolate the portions of the semiconductor region on either side of the fin isolation structure.

Abstract: Techniques are provided herein to form an integrated circuit with a standard cell layout that can utilize both frontside and backside connections along with power vias to provide either frontside or backside power rails to the circuit. The standard cell layout may include, for example, two total transistors with one transistor being an n-channel device with the other being a p-channel device. Power vias may be arranged at the boundaries of the standard cell layout, along with both frontside and backside connections to enable either frontside or backside compatible layouts for the power delivery. In some examples, each of the devices of the standard cell may be GAA transistors that each have a number of nanoribbons or other semiconductor bodies (e.g., one to four) extending in the same direction. Other standard cell layouts may include, for example, four total transistors arranged in a NAND or a NOR configuration.

Abstract: Techniques are provided herein to form an integrated circuit with a standard cell layout that can utilize both frontside and backside connections along with a tighter pitch between the devices. The standard cell layout may include two total transistors with one transistor being an n-channel device with the other being a p-channel device. A pitch between the transistors may be reduced compared to conventional layouts in part due to a reduction in a thickness of a shallow trench isolation (STI) layer. The thinner STI layer reduces the aspect ratio (AR) of backside contacts made beneath source or drain regions of the devices. In some such examples, each of the devices of the standard cell may be gate-all-around transistors each having any number of nanoribbons extending in the same direction. Other standard cell layouts may include four total transistors arranged in a NAND or a NOR configuration.

Abstract: Provided are a rotor structure and a motor. The rotor structure includes a rotor core, first permanent magnets, and a second permanent magnet, wherein the rotor core is provided with mounting grooves, and the first permanent magnets are mounted in the mounting grooves respectively; an axial height of the first permanent magnets is greater than an axial height of the rotor core; the second permanent magnet is disposed at an axial end of the rotor core and is of an integrated structure, through slots are disposed on the second permanent magnet, and at least one end of each of the first permanent magnets extends out of the rotor core in an axial direction and is inserted into a corresponding through slot; the second permanent magnet further includes an annular portion and magnetic pole portions, wherein the magnetic pole portions are integrally formed by a connection of the annular portion.

Abstract: Provided in the present disclosure is a method for feeding back channel state information, including: determining a neural network parameter, and constructing an encoder according to the neural network parameter; compressing channel information with the encoder to obtain channel state information; and feeding back the channel state information. Further provided in the present disclosure are a method for receiving channel state information, and a terminal, a base station, and a computer-readable storage medium.

Abstract: Described herein are a rotor structure and a motor. The rotor structure comprises a rotor core, first permanent magnets, and a second permanent magnet. The rotor core is provided with mounting grooves, and the first permanent magnets are mounted in the mounting grooves. Along an axial direction of the rotor core, the axial height of the first permanent magnet is greater than the axial height of the rotor core. The second permanent magnet has an integral structure and includes axial portions arranged at axial ends of the rotor core. The axial portions are provided with grooves, and the parts of the first permanent magnets extending out of the rotor core along the axial direction are inserted into the grooves.

Abstract: Disclosed herein are a rotor structure and a motor. The rotor structure includes: a rotor core including a plurality of axially stacked magnetic laminations, wherein under one pole of the rotor core, a plurality of conductor slots and multi-layer permanent magnet slots are disposed; and magnet steels, disposed in the permanent magnet slots. The rotor core includes a d-axis and a q-axis. Under one pole, the conductor slots including d-axis conductor slots and q-axis conductor slots. Under the same pole, the number of d-axis conductor slots located on the side of the magnet steels close to a rotor outer circumference is at least two, and a total length L5 of all the d-axis conductor slots in a direction perpendicular to the d-axis is greater than a length L1 of each of the magnet steels in the direction perpendicular to the d-axis, with 1.2?L5/L1?2.

Abstract: Disclosed herein are a permanent magnet assisted synchronous reluctance motor. The permanent magnet assisted synchronous reluctance motor includes a stator structure and a rotor structure. The stator structure is sleeved outside the rotor structure and forms an air gap with the rotor structure. The rotor structure includes a rotor core. The stator structure includes a stator core having uniformly distributed thereon a plurality of alternately arranged stator teeth and stator slots. When any d-axis centerline of the rotor structure is aligned with a stator tooth centerline of the stator structure, a d-axis centerline adjacent to the d-axis centerline is aligned with a stator slot centerline, and a q-axis centerline adjacent to the d-axis centerline is staggered with the stator tooth centerline or the stator slot centerline.

Abstract: A current detection method, a loss capacity prediction method, and a battery screening method for battery self-discharge are provided. In the current detection method for battery self-discharge, a battery is charged with a tiny current by a regulated power supply under a preset condition. During a charging process of the battery by using the regulated power supply, a charging current provided by the regulated power supply is adjusted until a voltage of the battery remains stable. When the voltage of the battery remains stable, the charging current is determined as a self-discharge current of the battery under the preset condition.

Abstract: A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.

Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

Abstract: Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

Abstract: Disclosed is a screening method for raw materials of high-yield sustainable aviation fuel, comprising the following steps: obtaining composition and content of fatty acid in different waste animal and vegetable oils; obtaining the theoretical limit yields of sustainable aviation fuel prepared from different fatty acids; calculating the theoretical yields of sustainable aviation fuel produced from different waste animal and vegetable oils as raw materials based on their fatty acid composition and content, as well as the theoretical limit yields of sustainable aviation fuel prepared from different fatty acids; selecting appropriate animal and vegetable oils as raw materials for producing sustainable aviation fuel based on the theoretical yields of sustainable aviation fuel. This disclosure provides guidance for enterprises to efficiently produce high-yield and high-value lipid-based bio-jet fuel.

Abstract: A seat assembly includes a seat base, a seat bottom connected to the seat base, a seat back pivotably connected to the seat base, and/or an adjustment assembly connected to the seat base. The adjustment assembly may include a first lever connected to the seat back, a second lever pivotably connected to the seat base and the seat back, and/or a motor coupled to the first lever. Actuation of the motor may rotate the first lever to adjust the seat back to a first seat position and to a second seat position relative to the seat base.

Abstract: An artificial intelligence based chatbot development system discloses a method including receiving from a user a configuration file including chatbot framework information for configuring a framework for a chatbot for a team of end users, the user configuration file including at least one of a name of a team, one or more document sites related to the team, one or more incident identifications searched by the team, determining a plurality of data sources relevant to the team based on the chatbot framework information, downloading a plurality of document chunks from the data sources relevant to the team, processing the plurality of document chunks to generate metadata tags related to the document chunks, vectorizing the metadata tags to generate metadata embeddings for the plurality of document chunks, and in response to receiving a user query, using the metadata embeddings to select a collection of the document chunks that are passed to a language model (LM) with the user query.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion; and an optical fiber coupled to the optical integrated device.