Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion; and an optical fiber coupled to the optical integrated device.

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

Abstract: An electronic device may have a display with an array of pixels. Each pixel may include inorganic light-emitting diodes of the same color such as a blue inorganic light-emitting diode. To emit different colors of light using the same type of inorganic light-emitting diodes, quantum dot layers may be used. Each quantum dot layer may have an associated reflective layer. Each light-emitting diode may also have an associated reflective layer. The reflective layer for the light-emitting diode may conform to the light-emitting diode or may be separated from the light-emitting diode by gap. When the reflective layer is separated from the light-emitting by a gap, the gap may be filled by a quantum dot layer or a diffusive layer.

Abstract: Optoelectronic structures and methods of assembly are described. In an embodiment, an optoelectronic structure includes a frontplane directly bonded to a backplane, and a cover window attached to the frontplane so that a cavity forms between the cover window and an optical layer of the frontplane. In an embodiment, the width of the cover window is less than the width of the backplane. In an embodiment, the width of the cover window is equal to the width of the backplane.

Abstract: Display structures and methods of assembly are described. In an embodiment, a display structure includes a display panel including a pattern of trenches extending at least partially through a backplane of the display panel, without extending past a matrix of LEDs in an overlying emission layer stack. The plurality of trenches can be formed in 2D to facilitate bending of the display panel into a 3D film curvature.

Abstract: The invention relates to an Oceanobacillus jeddahense strain HMF12, preservation number CGMCC No. 30478. The microbial inoculant contains 4×109 cfu/g to 7×109 cfu/g of Oceanobacillus jeddahense HMF12 spores. This strain can promote seed germination and plant growth under salt stress conditions and effectively prevent and control crop diseases, especially strawberry gray mold.

Abstract: A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.

Abstract: The present disclosure relates to an inverter system, a power allocation method and apparatus for an inverter system, a control apparatus, a storage medium, and a photovoltaic power station. The inverter system includes a plurality of inverters. A direct current side of each of the plurality of inverters is connected to a photovoltaic module, and alternating current sides of the plurality of inverters are connected in parallel. The method includes: obtaining an overload power of each of the plurality of inverters that is in an operating state and a capacity ratio of the photovoltaic module corresponding to each inverter; and allocating a total target active power of the inverter system based on the overload power and the capacity ratio to obtain a target active power of each of the plurality of inverters.

Abstract: Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.

Abstract: The present invention relates to a compound of chemical formula (I), and further relates to a preparation method therefor and use thereof. Pharmacological experiment results show that the compound of the present invention has excellent anti-tumor activity, good stability, low toxicity, and broad-spectrum efficacy, and can be used as an anti-tumor medicament, and provides a theoretical basis for subsequent research and development of drugs.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: A self-discharge screening method for lithium-ion batteries is provided. In the method, a single batch screening objects includes a plurality of trays. Each tray of the plurality of trays includes a plurality of batteries to be screened. Voltage drops per unit time of the plurality of batteries to be screened are measured. Voltage drop screening thresholds of the plurality of trays are determined according to the measured voltage drops per unit time. Unqualified batteries are screened out according to a relative relationship between the voltage drop screening threshold of the tray and the voltage drops per unit time of the plurality of batteries.

Abstract: Techniques are provided herein to form an integrated circuit with a double-height standard cell layout that can utilize both frontside and backside connections. The layout involves merging two of the transistors into a single wider transistor that extends along the midline of the double-height standard cell layout. Accordingly, the double-height standard cell layout may include three total transistors with one transistor being wider than the other two. The transistors may be configured as an inverter with enhanced driving capability in the double height standard cell layout. The wider transistor at the center of the double-height standard cell layout includes a source or drain region with both a topside contact and a backside contact to provide additional interconnect routing flexibility. The double-height standard cell may include an n-channel device having a first width aligned along a centerline of the double-height standard cell and two p-channel devices or vice versa.

Abstract: Techniques are provided herein to form semiconductor devices within a standard unit cell having topside metal tracks that are offset from backside metal tracks. Stacked transistors are provided such that a source or drain region of one device is located vertically over the source or drain region of the other device. Both frontside and backside contacts may be formed to contact either top or bottom surfaces of the corresponding source or drain regions. Topside metal tracks are used to provide signal and power to various transistor elements of the top semiconductor device while backside metal tracks are used to provide signal and power to various transistor elements of the bottom semiconductor device. The topside tracks are offset from the backside tracks such that one topside track is aligned along one boundary of a standard unit cell and one backside track is aligned along the opposite standard unit cell boundary.

Abstract: The invention relates to an Oceanobacillus jeddahense strain HMF12, preservation number CGMCC No. 30478. The microbial inoculant contains 4×109 cfu/g to 7×109 cfu/g of Oceanobacillus jeddahense HMF12 spores. This strain can promote seed germination and plant growth under salt stress conditions and effectively prevent and control crop diseases, especially strawberry gray mold.

Abstract: Techniques are provided herein to form an integrated circuit having stacked semiconductor devices with their source or drain regions coupled together via matching backside connections. In an example, FET (field effect transistor) devices may be formed on two different substrates and bonded together at their backsides such that backside contacts beneath each device substantially align at or near the bonding interface. The substrate beneath both the first FET and the second FET is removed, and backside contacts are formed beneath the source or drain regions of the first and second FETs. A bonding layer may also be formed on the backside of either the first FET or the second FET. The second FET is then flipped upside down and bonded to the backside of the first FET, such that the backside contacts from the first and second FET's are substantially aligned and are conductively coupled through the bonding layer.

Abstract: The present disclosure relates to a compound, a material for an organic electroluminescent device and an application thereof. The compound has a structure represented by Formula (1). The compound has a relatively high refractive index in the region of visible light (400-750 nm), which is conducive to improving the light-emitting efficiency.

Abstract: Dual core LED structures and methods of fabrication are described in which serial diodes are integrated into a single dual core LED chip. In some configurations serial diodes are integrated in a side-by-side configuration and separated by a trench. In other configurations the serial diodes are vertically integrated, and may be assembled using a wafer-on-wafer processing sequence.

Abstract: An electronic device may include a display having a monolithic array of light-emitting diodes mounted to a surface of a substrate layer. The diodes may include contact pads. Driver circuitry may independently drive each of the diodes in the array using drive signals. The driver circuitry may be formed on a driver integrated circuit. Bond pads may be formed on a surface of the integrated circuit. Copper pillars may be grown on the bond pads. In another suitable arrangement, the driver circuitry may be formed on a driver printed circuit board coupled to an interposer by a flexible printed circuit. The interposer may include bond pads and copper pillars grown on the bond pads. The contact pads on each of the diodes may be simultaneously bonded to the copper pillars. A surface of the substrate layer may be patterned to form light redirecting elements if desired.