Abstract: Described herein are a rotor structure and a motor. The rotor structure comprises a rotor core, first permanent magnets, and a second permanent magnet. The rotor core is provided with mounting grooves, and the first permanent magnets are mounted in the mounting grooves. Along an axial direction of the rotor core, the axial height of the first permanent magnet is greater than the axial height of the rotor core. The second permanent magnet has an integral structure and includes axial portions arranged at axial ends of the rotor core. The axial portions are provided with grooves, and the parts of the first permanent magnets extending out of the rotor core along the axial direction are inserted into the grooves.

Abstract: Disclosed herein are a rotor structure and a motor. The rotor structure includes: a rotor core including a plurality of axially stacked magnetic laminations, wherein under one pole of the rotor core, a plurality of conductor slots and multi-layer permanent magnet slots are disposed; and magnet steels, disposed in the permanent magnet slots. The rotor core includes a d-axis and a q-axis. Under one pole, the conductor slots including d-axis conductor slots and q-axis conductor slots. Under the same pole, the number of d-axis conductor slots located on the side of the magnet steels close to a rotor outer circumference is at least two, and a total length L5 of all the d-axis conductor slots in a direction perpendicular to the d-axis is greater than a length L1 of each of the magnet steels in the direction perpendicular to the d-axis, with 1.2?L5/L1?2.

Abstract: Disclosed herein are a permanent magnet assisted synchronous reluctance motor. The permanent magnet assisted synchronous reluctance motor includes a stator structure and a rotor structure. The stator structure is sleeved outside the rotor structure and forms an air gap with the rotor structure. The rotor structure includes a rotor core. The stator structure includes a stator core having uniformly distributed thereon a plurality of alternately arranged stator teeth and stator slots. When any d-axis centerline of the rotor structure is aligned with a stator tooth centerline of the stator structure, a d-axis centerline adjacent to the d-axis centerline is aligned with a stator slot centerline, and a q-axis centerline adjacent to the d-axis centerline is staggered with the stator tooth centerline or the stator slot centerline.

Abstract: A current detection method, a loss capacity prediction method, and a battery screening method for battery self-discharge are provided. In the current detection method for battery self-discharge, a battery is charged with a tiny current by a regulated power supply under a preset condition. During a charging process of the battery by using the regulated power supply, a charging current provided by the regulated power supply is adjusted until a voltage of the battery remains stable. When the voltage of the battery remains stable, the charging current is determined as a self-discharge current of the battery under the preset condition.

Abstract: A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.

Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

Abstract: Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

Abstract: Disclosed is a screening method for raw materials of high-yield sustainable aviation fuel, comprising the following steps: obtaining composition and content of fatty acid in different waste animal and vegetable oils; obtaining the theoretical limit yields of sustainable aviation fuel prepared from different fatty acids; calculating the theoretical yields of sustainable aviation fuel produced from different waste animal and vegetable oils as raw materials based on their fatty acid composition and content, as well as the theoretical limit yields of sustainable aviation fuel prepared from different fatty acids; selecting appropriate animal and vegetable oils as raw materials for producing sustainable aviation fuel based on the theoretical yields of sustainable aviation fuel. This disclosure provides guidance for enterprises to efficiently produce high-yield and high-value lipid-based bio-jet fuel.

Abstract: A seat assembly includes a seat base, a seat bottom connected to the seat base, a seat back pivotably connected to the seat base, and/or an adjustment assembly connected to the seat base. The adjustment assembly may include a first lever connected to the seat back, a second lever pivotably connected to the seat base and the seat back, and/or a motor coupled to the first lever. Actuation of the motor may rotate the first lever to adjust the seat back to a first seat position and to a second seat position relative to the seat base.

Abstract: An artificial intelligence based chatbot development system discloses a method including receiving from a user a configuration file including chatbot framework information for configuring a framework for a chatbot for a team of end users, the user configuration file including at least one of a name of a team, one or more document sites related to the team, one or more incident identifications searched by the team, determining a plurality of data sources relevant to the team based on the chatbot framework information, downloading a plurality of document chunks from the data sources relevant to the team, processing the plurality of document chunks to generate metadata tags related to the document chunks, vectorizing the metadata tags to generate metadata embeddings for the plurality of document chunks, and in response to receiving a user query, using the metadata embeddings to select a collection of the document chunks that are passed to a language model (LM) with the user query.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion; and an optical fiber coupled to the optical integrated device.

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

Abstract: An electronic device may have a display with an array of pixels. Each pixel may include inorganic light-emitting diodes of the same color such as a blue inorganic light-emitting diode. To emit different colors of light using the same type of inorganic light-emitting diodes, quantum dot layers may be used. Each quantum dot layer may have an associated reflective layer. Each light-emitting diode may also have an associated reflective layer. The reflective layer for the light-emitting diode may conform to the light-emitting diode or may be separated from the light-emitting diode by gap. When the reflective layer is separated from the light-emitting by a gap, the gap may be filled by a quantum dot layer or a diffusive layer.

Abstract: Optoelectronic structures and methods of assembly are described. In an embodiment, an optoelectronic structure includes a frontplane directly bonded to a backplane, and a cover window attached to the frontplane so that a cavity forms between the cover window and an optical layer of the frontplane. In an embodiment, the width of the cover window is less than the width of the backplane. In an embodiment, the width of the cover window is equal to the width of the backplane.

Abstract: Display structures and methods of assembly are described. In an embodiment, a display structure includes a display panel including a pattern of trenches extending at least partially through a backplane of the display panel, without extending past a matrix of LEDs in an overlying emission layer stack. The plurality of trenches can be formed in 2D to facilitate bending of the display panel into a 3D film curvature.

Abstract: The invention relates to an Oceanobacillus jeddahense strain HMF12, preservation number CGMCC No. 30478. The microbial inoculant contains 4×109 cfu/g to 7×109 cfu/g of Oceanobacillus jeddahense HMF12 spores. This strain can promote seed germination and plant growth under salt stress conditions and effectively prevent and control crop diseases, especially strawberry gray mold.

Abstract: A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.