Patents by Inventor Xia Li

Xia Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289989
    Abstract: The present disclosure belongs to technical field of OLEDs, and provides a compound suitable as a hole transport material and an electron blocking material of OLEDs. The compound has a general structure according to [Chemical Formula 1], in which Ar1 and Ar2 are each independently selected from a hydrogen atom, a substituted or unsubstituted C5-C40 aryl, or a substituted or unsubstituted C5-C40 heteroaryl; m and n are each an integer independently selected from 0, 1, or 2; X is selected from O, S, or —NR—; R is selected from hydrogen, or a substituted or unsubstituted C5-C40 aryl; Ar3 has a structure according to [Chemical Formula 2], in which R1-R8 are each independently selected from a hydrogen atom, or a substituted or unsubstituted C5-C40 aryl; Y is selected from O, S, or —NR?—; and R? is selected from a hydrogen atom, or a substituted or unsubstituted C5-C40 aryl.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 29, 2025
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Lei Zhang, Wei Gao, Jinghua Niu, Wenpeng Dai, Wenjing Xiao, Xia Li
  • Patent number: 12277693
    Abstract: Systems, devices, methods, and computer readable medium for evaluating visual quality of digital content are disclosed. Methods can include training machine learning models on images. A request is received to evaluate quality of an image included in a current version of a digital component generated by the computing device. The machine learning models are deployed on the image to generate a score for each quality characteristic of the image. A weight is assigned to each score to generate weighted scores. The weighted scores are combined to generate a combined score for the image. The combined score is compared to one or more thresholds to generate a quality of the image.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: April 15, 2025
    Assignee: Google LLC
    Inventors: Catherine Shyu, Xiyang Luo, Feng Yang, Junjie Ke, Yicong Tian, Chao-Hung Chen, Xia Li, Luying Li, Wenjing Kang, Shun-Chuan Chen
  • Publication number: 20250109846
    Abstract: The invention discloses an integrated infrared sensing device for controlling a light source and a using method thereof. The integrated infrared sensing device comprises a housing and a mounting base arranged in the housing, wherein a sensitivity adjusting key, at least one infrared sensing probe and a control circuit board are arranged on the mounting base, the infrared sensing probes enable 360-degree sensing of humans or objects, the sensitivity adjusting key can adjust the sensing distance of the infrared sensing probe, and the control circuit board controls the on/off of the light source after receiving a sensing signal from the infrared sensing probe.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventor: Xia Li
  • Publication number: 20250107157
    Abstract: An electronic device having one or more Gate-All-Around GAA transistors is disclosed. At least one of the one or more GAA transistors comprises one or more inner gate structures having a work function metal bounded by a gate dielectric; and one or more inner gate spacers associated with the one or more inner gate structures, wherein each of the one or more inner gate structures has a generally concave outer edge that conforms to a generally convex inner edge of an associated inner gate spacer of the one or more inner gate spacers.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 27, 2025
    Inventors: Xia LI, Junjing BAO, Biswa Ranjan PANDA
  • Publication number: 20250107200
    Abstract: An electronic device having one or more non-planar transistors is disclosed. At least one of the non-planar transistors comprises: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising an interior wall disposed next to a respective gate structure of the one or more gate structures, wherein the interior wall is formed from a first dielectric material, an exterior wall spaced apart from the interior wall, wherein the exterior wall is formed from a second dielectric material, and a third dielectric material disposed between the interior wall and the exterior wall, wherein a dielectric constant of the third dielectric material is lower than both the dielectric constants of the first and second dielectric materials.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Inventors: Xia LI, Junjing BAO, Biswa Ranjan PANDA
  • Patent number: 12261492
    Abstract: The present disclosure provides a rotor structure, an electric motor and a rotor manufacturing method. The rotor structure includes a plurality of rotor sheets (100) and a rotating shaft. The rotor sheets (100) are stacked in sequence along an axial direction of the rotor structure. Each of the rotor sheets (100) is provided with a shaft hole (20), a first slot (111), and first filling slots (121) at both ends of the first slot (111). The first slot (111) extends in a direction of a direct axis (3) of the rotor structure and includes slot sections (1110) at opposite sides of the shaft hole (20). The rotating shaft passes through the shaft hole (20) of the plurality of rotor sheets (100). The first slot (111), the first filling slots (121) and the rotating shaft form a first flux barrier layer (101).
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 25, 2025
    Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Yusheng Hu, Bin Chen, Yong Xiao, Jinfei Shi, Xia Li, Zhidong Zhang
  • Publication number: 20250096661
    Abstract: A self-starting synchronous reluctance compressor and a refrigeration device system. The self-starting synchronous reluctance compressor includes a cylinder, a flange, a muffling cover, and a motor. The motor comprises a motor rotor. The flange is connected to the cylinder, and the muffling cover is arranged on the flange. A muffling cavity is formed between the muffling cover and the flange, and at least one exhaust port is disposed in the muffling cover. Multiple layers of rotor slots are arranged on the motor rotor, and at least part of the rotor slots axially penetrates the motor rotor. A total cross-sectional area of the at least part of the rotor slots axially penetrating the motor rotor is Sx, and a total cross-sectional area of the at least one exhaust port is Ss, and it is satisfied that Sx>Ss.
    Type: Application
    Filed: October 28, 2022
    Publication date: March 20, 2025
    Applicant: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Yusheng HU, Bin CHEN, Yong XIAO, Jinfei SHI, Xia LI
  • Publication number: 20250091495
    Abstract: The present application relates to a seat assembly and an adjustable armrest assembly. An adjustable armrest assembly may include an armrest mount, an armrest, and an armrest adjuster. The armrest may be adjustably connected to the armrest mount. The armrest adjuster may be pivotably connected to the armrest and the armrest mount. The armrest adjuster may be pivotably connectable to a seat of a seat assembly. The armrest adjuster may adjust the armrest relative to the armrest mount to (i) an extended position when said seat is adjusted to a first seat position and (ii) a retracted position when said seat is adjusted to a second seat position.
    Type: Application
    Filed: September 18, 2024
    Publication date: March 20, 2025
    Inventors: Minghao Yan, Bin Lu, Shuanghua Yang, Xia Li, Yue Zuo
  • Patent number: 12254799
    Abstract: A display system of a display includes multiple primary light emitting diodes and multiple secondary light emitting diodes. The multiple primary light emitting diodes may emit light, in which at least a first primary light emitting diode of the multiple primary light emitting diodes is shorted. Moreover, the multiple secondary light emitting diodes may emit light. At least a first secondary light emitting diode of the multiple secondary light emitting diodes is associated with the first primary light emitting diode, and the first secondary light emitting diode may emit light based at least in part on the first primary light emitting diode being shorted.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: March 18, 2025
    Assignee: Apple Inc.
    Inventors: Thomas Charisoulis, Saif Choudhary, Xia Li, Tore Nauta, Kapil V Sakariya
  • Publication number: 20250079337
    Abstract: An integrated circuit (IC) includes a plurality of first metallization layers on a front side of a circuit layer and a plurality of second metallization layers on a back side of the circuit layer. A semiconductor substrate on the back side of the circuit layer of the IC is thinned to improve access to devices from the back side. The plurality of second metallization layers are employed to provide increased interconnection among the devices without increasing area and may provide increased access to external contacts. Thinning the semiconductor substrate reduces structural rigidity needed for processing, so the IC also includes a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers to increase rigidity and first vias extending through the stiffening layer to couple to first contacts.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Xia Li, Jonghae Kim, Bin Yang, Giridhar Nallapati
  • Publication number: 20250072105
    Abstract: An integrated circuit (IC) device includes an N-type field effect transistor (FET). The N-type FET includes an N-type vertical structure on a substrate, including an N-type gate region having a first normal-k oxide layer on a semiconductor layer of the N-type vertical structure, an N-type work-function metal (WFM) layer on the first normal-k oxide layer and sidewall spacers of the N-type gate region, and a first metal gate on the N-type WFM layer. The IC device includes a first P-type FET. The first P-type FET includes a first P-type vertical structure on the substrate, including a first P-type gate region having a second normal-k oxide layer on a first semiconductor layer of the first P-type vertical structure, a first P-type WFM layer on the second normal-k oxide layer and sidewall spacers of the first P-type gate region, and a second metal gate on the first P-type WFM layer.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Inventors: Xia LI, Junjing BAO, Biswa Ranjan PANDA, Ramesh MANCHANA
  • Patent number: 12234977
    Abstract: A flame retardant lamp includes a lamp body, a printed circuit board (PCB), a power supply, a light-emitting plate, a controller, a driving circuit, and a first temperature sensor. The PCB, the power supply, and the light-emitting plate are disposed inside the lamp body, the controller and the driving circuit are disposed on the PCB, and the first temperature sensor is disposed on the light-emitting plate. The controller is electrically connected to the light-emitting plate through the driving circuit, the first temperature sensor is electrically connected to an input end of the controller, and the power supply is electrically connected to a power supply end of the PCB.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: February 25, 2025
    Assignee: POWER ON TOOLS CO., LTD
    Inventors: Xun Chen, Zhangxun Weng, Xia Li, Yvbing Zhu, Kongjing Lin, William Joseph Tadda, Jr.
  • Patent number: 12224347
    Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 11, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bin Yang, Xia Li, Haining Yang
  • Patent number: 12206287
    Abstract: A single-phase permanent magnet synchronous motor and dust collector. The single-phase permanent magnet synchronous motor includes a plurality of stator teeth, the plurality of stator teeth include at least: a first-type and second-type stator tooth; the first-type and second-type stator teeth enclose an annular working cavity for accommodating a rotor part, where the size of a central angle corresponding to a first contour line of an end face of the first-type stator tooth facing the rotor part is different from the size of a central angle corresponding to a second contour line of an end face of the second-type stator tooth facing the rotor part. The motor has a significantly reduced cogging torque, a greatly reduced torque ripple, and an obviously increased motor output torque. The single-phase permanent magnet synchronous motor is small in size, light in weight, simple in structure, convenient for large-scale manufacture and low in manufacturing cost.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 21, 2025
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Yusheng Hu, Bin Chen, Yong Xiao, Zhidong Zhang, Jinfei Shi, Shengyu Xiao, Xia Li, Lin Tang, Shaoxuan Zhu, Pengqian Gui, Hui Sun, Jiating Ding
  • Patent number: 12206001
    Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 21, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bin Yang, Haining Yang, Xia Li
  • Publication number: 20250022407
    Abstract: A pulse width modulation and amplitude modulation driving system for a display panel, including related circuits and methods of operation, are described. In an embodiment, a display panel includes a thin film transistor layer comprising a plurality of subpixel circuits. Each subpixel circuit may include a drive transistor, a comparator, and a switch. A plurality of light emitting diodes (LEDs), such as micro-LEDs, may be connected to the plurality of subpixel circuits. Each subpixel circuit can control an LED based on a current amplitude controlled by the drive transistor and a current pulse width controlled by the comparator and the switch. Other aspects are also described and claimed.
    Type: Application
    Filed: June 13, 2024
    Publication date: January 16, 2025
    Inventors: Majid Gharghi, Tore Nauta, Saif Choudhary, Chuang Qian, Hopil Bae, Mahdi Farrokh Baroughi, Xia Li, Patrick B Bennett, Ze Yuan
  • Publication number: 20250024745
    Abstract: This application provides a display assembly and an electronic device. The display assembly includes: a display panel, a polarizer, and a heat dissipation film. The display panel includes a substrate and a plurality of light emitting devices located on a side of the substrate. The polarizer is located on a side of the light emitting device away from the substrate. The heat dissipation film is located on a side of the display panel away from the polarizer. The polarizer includes at least one electrostatic dissipation layer, or the heat dissipation film includes at least one electrostatic dissipation layer. The electrostatic dissipation layer is configured to guide static electricity into the electrostatic dissipation layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 16, 2025
    Inventors: Xun Lao, Menghu Shen, Haisu Han, Xia Li, Zhaoyu Teng, Xiaotao Dai
  • Publication number: 20250024735
    Abstract: A display panel comprises a hole, a transition region, and an image display region. A display layer of the display panel is located on a side of a substrate and includes a first cathode portion. The display panel further includes an isolation column located in the transition region, and a first film layer is in contact with the isolation column. The isolation column includes an insulation isolation portion. A part of a side wall of the insulation isolation portion is recessed toward an inside of the insulation isolation portion to form a groove. A first surface of a side of the insulation isolation portion is away from the substrate. The first cathode portion extending on the first film layer is separated at the groove from the first cathode portion extending on the first surface.
    Type: Application
    Filed: November 2, 2022
    Publication date: January 16, 2025
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xun Lao, Menghu Shen, Haisu Han, Xia Li, Xiaotao Dai, Yuling Xu
  • Publication number: 20240429141
    Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Xia LI, Xuefeng ZHANG, Aniket PATIL
  • Publication number: 20240421157
    Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region to improve carrier mobility, thereby increasing drive strength. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region to further improve carrier mobility. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Xia Li, Ming-Huei Lin, Haining Yang