Abstract: Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Abstract: A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

Abstract: A refrigerator drawer assembly, comprising: a drawer body, the drawer body comprising a front wall and a rear wall arranged opposite to each other along the pulling direction thereof, and defining an accommodating cavity used for placing articles, wherein the front wall is provided with two first sliding grooves extending along the horizontal direction and running along the thickness direction thereof, and the rear wall is provided with two second sliding grooves aligned with the two first sliding grooves; and two sliding partition assemblies, wherein two ends of each sliding partition assembly are inserted into a set of a first sliding groove and a second sliding groove that are aligned, and the two sliding partition assemblies are configured to be able to slide along the first sliding grooves and the second sliding grooves and are capable of sliding to a fitted state.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Abstract: A refrigerator drawer assembly, comprising: a drawer body, the drawer body comprising a front wall and a rear wall arranged opposite to each other along the pulling direction thereof, and defining an accommodating cavity used for placing articles, wherein the front wall is provided with two first sliding grooves extending along the horizontal direction and running along the thickness direction thereof, and the rear wall is provided with two second sliding grooves aligned with the two first sliding grooves; and two sliding partition assemblies, wherein two ends of each sliding partition assembly are inserted into a set of a first sliding groove and a second sliding groove that are aligned, and the two sliding partition assemblies are configured to be able to slide along the first sliding grooves and the second sliding grooves and are capable of sliding to a fitted state.

Abstract: The present invention relates to novel compounds of formula (I), wherein R1, R2, R3, R4, R5 and R6 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: The present invention relates to novel compounds of formula (I), wherein R1 to R7 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Abstract: The present invention relates to novel compounds of formula (I), wherein R1, R2, R3, R4, R5, R6 and R7 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Abstract: The present invention relates to novel compounds of formula (I) or (II), wherein R1 to R6, R11 to R17 are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Abstract: Disclosed are substituted fused pyrazoles, for example substituted indazoles, that inhibit LRRK2 kinase activity, pharmaceutical compositions containing them and their use in the treatment of Parkinson's disease.

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Abstract: An air supply assembly for a refrigerator, includes: an air duct cover plate defining, together with a refrigerator liner, an air supply space and configured to isolate the air supply space from a storage space in a compartment of the refrigerator, and a centrifugal wind wheel arranged in the air supply space, and axially sucking air in and blowing the air out towards a peripheral side, wherein a plurality of air return ports are provided in the air duct cover plate to allow air in the storage space to enter the air supply space; and the centrifugal wind wheel abuts against an inner side of the air duct cover plate and is configured to suck air in from a rear side thereof, such that air entering the air supply space via the air return ports is sucked in from the rear side of the centrifugal wind wheel.

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.