Patents by Inventor Xiao DING

Xiao DING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210238197
    Abstract: The present invention relates to novel compounds of formula (I), wherein R1, R2, R3, R4, R5, R6 and R7 are as described herein, and their pharmaceutically acceptable salt, enantiomer or diastereomer thereof, and compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: November 25, 2020
    Publication date: August 5, 2021
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Fabian Dey, Xiao Ding, Yimin Hu, Yongqiang Liu, Hong Shen, Houguang Shi, Xuefei Tan, Chengang Zhou, Mingwei Zhou
  • Patent number: 11080457
    Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Derong Liu, Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Publication number: 20210221832
    Abstract: The present invention relates to novel compounds of formula (I) or (II), wherein R1 to R6, R11 to R17 are as described herein, and their pharmaceutically acceptable salt thereof, and compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 22, 2021
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Xiao DING, Yongqiang LIU, Hong SHEN, Houguang SHI, Xuefei TAN, Chengang ZHOU, Mingwei ZHOU
  • Patent number: 11030378
    Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10975081
    Abstract: Disclosed are substituted fused pyrazoles, for example substituted indazoles, that inhibit LRRK2 kinase activity, pharmaceutical compositions containing them and their use in the treatment of Parkinson's disease.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 13, 2021
    Assignee: GLAXOSMITHKLINE INTELLECTUAL PROPERTY DEVELOPMENT LIMITED
    Inventors: Xiao Ding, Yun Jin, Qian Liu, Feng Ren, Yingxia Sang, Luigi Piero Stasi, Zehong Wan, Hailong Wang, Weiqiang Xing, Yang Zhan, Baowei Zhao
  • Patent number: 10963620
    Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 30, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Jhih-Rong Gao, Zhuo Li
  • Publication number: 20210063074
    Abstract: An air supply assembly for a refrigerator, includes: an air duct cover plate defining, together with a refrigerator liner, an air supply space and configured to isolate the air supply space from a storage space in a compartment of the refrigerator, and a centrifugal wind wheel arranged in the air supply space, and axially sucking air in and blowing the air out towards a peripheral side, wherein a plurality of air return ports are provided in the air duct cover plate to allow air in the storage space to enter the air supply space; and the centrifugal wind wheel abuts against an inner side of the air duct cover plate and is configured to suck air in from a rear side thereof, such that air entering the air supply space via the air return ports is sucked in from the rear side of the centrifugal wind wheel.
    Type: Application
    Filed: January 8, 2019
    Publication date: March 4, 2021
    Applicant: HAIER SMART HOME CO., LTD.
    Inventors: Ning WANG, Guangrui WU, Hongliang LI, Penghui LI, Xiao DING, Chang LIU, Chaoge XU, Xing LIANG, Qing CHEN
  • Patent number: 10936777
    Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jhih-Rong Gao, Yi-Xiao Ding, Zhuo Li
  • Publication number: 20210024916
    Abstract: Compositions and methods for using nucleosome interacting protein domains to increase accessibility of programmable DNA modification proteins to target chromosomal sequences, thereby increasing efficiency of targeted genome/epigenetic modification in eukaryotic cells.
    Type: Application
    Filed: February 18, 2020
    Publication date: January 28, 2021
    Inventors: Fuqiang Chen, Xiao Ding, Yongmei Feng, Gregory Davis
  • Publication number: 20200392158
    Abstract: The present invention relates to novel compounds that inhibit LRRK2 kinase activity, to processes for their preparation, to compositions containing them and to their use in the treatment of or prevention of diseases associated with or characterized by LRRK2 kinase activity, for example Parkinson's disease, Alzheimer's disease and amyotrophic lateral sclerosis (ALS).
    Type: Application
    Filed: July 12, 2018
    Publication date: December 17, 2020
    Inventors: Xiao DING, Ming-Hsun HO, Feng REN, Haihua YU, Yang ZHAN
  • Patent number: 10860764
    Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Jhih-Rong Gao, Zhuo Li
  • Patent number: 10858367
    Abstract: Provided are novel compounds that inhibit LRRK2 kinase activity, processes for their preparation, compositions containing them and their use in the treatment of or prevention of diseases associated with or characterized by LRRK2 kinase activity, for example Parkinson's disease, Alzheimer's disease and amyotrophic lateral sclerosis (ALS).
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 8, 2020
    Assignee: GLAXOSMITHKLINE INTELLECTUAL PROPERTY DEVELOPMENT LIMITED
    Inventors: Xiao Ding, Feng Ren, Yingxia Sang, Weiqiang Xing, Yang Zhan, Baowei Zhao
  • Patent number: 10706201
    Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz
  • Publication number: 20200208135
    Abstract: Compositions and methods for using nucleosome interacting protein domains to increase accessibility of programmable DNA modification proteins to target chromosomal sequences, thereby increasing efficiency of targeted genome/epigenetic modification in eukaryotic cells.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 2, 2020
    Inventors: Fuqiang Chen, Xiao Ding, Yongmei Feng, Gregory Davis
  • Patent number: 10685164
    Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 16, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10618901
    Abstract: The present invention relates to novel compounds that inhibit LRRK2 kinase activity, processes for their preparation, to compositions containing them and to their use in the treatment of or prevention of diseases characterized by LRRK2 kinase activity, for example Parkinson's disease, Alzheimer's disease and amyotrophic lateral sclerosis (ALS).
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 14, 2020
    Assignee: GLAXOSMITHKLINE INTELLECTUAL PROPERTY DEVELOPMENT LIMITED
    Inventors: Xiao Ding, Qian Liu, Yingxia Sang, Luigi Piero Stasi, Zehong Wan, Baowei Zhao, Colin Michael Edge
  • Patent number: 10604752
    Abstract: Compositions and methods for using nucleosome interacting protein domains to increase accessibility of programmable DNA modification proteins to target chromosomal sequences, thereby increasing efficiency of targeted genome/epigenetic modification in eukaryotic cells.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 31, 2020
    Assignee: Sigma-Aldrich Co. LLC
    Inventors: Fuqiang Chen, Xiao Ding, Yongmei Feng, Gregory D. Davis
  • Publication number: 20200079777
    Abstract: Disclosed are novel compounds that inhibit LRRK2 kinase activity, processes for their preparation, compositions containing them and their use in the treatment of or prevention of diseases characterized by LRRK2 kinase activity, for example Parkinson's disease, Alzheimer's disease and amyotrophic lateral sclerosis (ALS).
    Type: Application
    Filed: July 22, 2016
    Publication date: March 12, 2020
    Applicant: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: Xiao DING, Yun JIN, Qian LIU, Feng REN, Yingxia SANG, Luigi Piero STASI, Zehong WAN, Hailong WANG, Weiqiang XING, Yang ZHAN, Baowei ZHAO
  • Patent number: 10509878
    Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Zhuo Li, Wen-Hao Liu
  • Patent number: D872138
    Type: Grant
    Filed: June 10, 2018
    Date of Patent: January 7, 2020
    Assignee: QINGDAO HAIER JOINT STOCK CO., LTD.
    Inventors: Xiao Ding, Ning Wang, Guangrui Wu