Patents by Inventor Xiaobin Wang

Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140213829
    Abstract: A method for producing methoxypolyethylene glycols includes the following steps: (1) after the reactor is washed by water, nitrogen is filled in the reactor to elevate the pressure and then the reactor is vacuumized to completely remove water and reduce the oxygen content in the reactor; (2) nitrogen is filled in the rector and pressure is elevated, and then methanol and sodium methoxide as the catalyst in methanol is added into the reactor, and then warming up; (3) ethylene oxide is added into the reactor at 800˜1200 kg/h to process the pre-reaction; (4) ethylene oxide is added into the reactor at 8000˜12000 kg/h to process the reaction after methanol and ethylene oxide in the reactor are completely reacted; (5) the pressure of reaction product is reduced and pH of reaction product is adjusted to 5˜7 after the reaction is finished, and then the reaction product is transferred to the tank yard.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 31, 2014
    Applicant: Xiamen Ju Sheng Mechanical Engineering Co., Ltd.
    Inventors: I-Min TSAI, Kun LI, Yanzhen HUANG, Xiaobin WANG, Kechang LI, Weiming WU
  • Patent number: 8792264
    Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
  • Patent number: 8780619
    Abstract: An apparatus and method for storing data in a semiconductor memory. In accordance with some embodiments, the semiconductor memory has a continuous storage layer of soft ferromagnetic material having opposing top and bottom surfaces with overall length and width dimensions and an overall thickness dimension between the opposing top and bottom surfaces. A plurality of spaced apart, discrete reference layers are adjacent a selected one of the opposing top or bottom surfaces of the continuous storage layer with each having a fixed magnetic orientation. A plurality of spaced apart, discrete barrier layers are disposed in contacting relation between the discrete reference layers and the continuous storage layer.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 15, 2014
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Yuankai Zheng, Xiaobin Wang, Dimitar V. Dimitrov, Pat J. Ryan
  • Publication number: 20140183608
    Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.
    Type: Application
    Filed: March 5, 2014
    Publication date: July 3, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Huadong Gan, Yiming Huai, Xiaobin Wang, Yuchen Zhou, Zihui Wang
  • Publication number: 20140167212
    Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
  • Patent number: 8742518
    Abstract: A magnetic tunnel junction device includes a reference magnetic layer and a magnetic free layer including first and second magnetic elements that are magnetically exchange coupled. The magnetic exchange coupling between the first and second magnetic elements is configured to achieve a switching current distribution less than about 200% and a long term thermal stability criterion of greater than about 60 kBT.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: June 3, 2014
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Kaizhong Gao
  • Patent number: 8729601
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 20, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8728890
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 20, 2014
    Assignee: Alpha & Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 8697520
    Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Alpha & Omega Semiconductor Incorporationed
    Inventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
  • Patent number: 8692322
    Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
    Type: Grant
    Filed: August 26, 2012
    Date of Patent: April 8, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pan, Daniel Ng, Anup Bhalla, Xiaobin Wang
  • Publication number: 20140042490
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.
    Type: Application
    Filed: October 21, 2013
    Publication date: February 13, 2014
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20140042571
    Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 13, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Xiaobin Wang, Zihui Wang, Bing K Yen
  • Patent number: 8642429
    Abstract: A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Xiaobin Wang, Anup Bhalla, Yeeherg Lee
  • Patent number: 8637368
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 28, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Xiaobin Wang
  • Publication number: 20140022837
    Abstract: Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a “0” or “1” bit can be managed, such as by an addition of DC biasing to the AC current.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 23, 2014
    Applicant: Seagate Technology LLC
    Inventors: Xiaobin Wang, Wenzhong Zhu, Henry Huang, Yiran Chen, Haiwen Xi
  • Publication number: 20140011053
    Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
    Type: Application
    Filed: August 6, 2013
    Publication date: January 9, 2014
    Applicant: Seagate Technology LLC
    Inventors: Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
  • Publication number: 20130329490
    Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
  • Publication number: 20130328121
    Abstract: A semiconductor power device includes a thick bottom insulator formed in a lower portion of a trench in a semiconductor epitaxial region. An electrically conductive gate electrode is formed in the trench above the bottom insulator. The gate electrode is electrically insulated from the epitaxial region by the bottom insulator and a gate insulator. Charge is deliberately induced in the thick bottom insulator proximate an interface between the bottom insulator and the epitaxial semiconductor region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Inventors: Xiaobin Wang, Anup Bhalla, Daniel Ng
  • Patent number: 8598623
    Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20130295415
    Abstract: Approaches to reduce switching field distribution in energy assisted magnetic storage devices involve first and second exchange coupled magnetic elements. The first magnetic elements have anisotropy, Hk1, volume, V1 and the second magnetic elements are magnetically exchange coupled to the first magnetic elements and have anisotropy Hk2, and volume V2. The thermal stability of the exchange coupled magnetic elements is greater than about 60 kBT at a storage temperature of about 300 K. The magnetic switching field distribution, SFD, of the exchange coupled magnetic elements is less than about 200% at a predetermined magnetic switching field and a predetermined assisting switching energy.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Xiaobin Wang, Kaizhong Gao