Abstract: A system, vehicle, and method for controlling a vehicle using geo-fence-based activity regulations that change over time. The system includes processor(s) configured to receive a geo-fence identifier that uniquely identifies a geo-fence, obtain one or more activity regulations for the vehicle based on the geo-fence identifier, and control operation of the vehicle according to a set of activity regulations applicable based on a current time. The activity regulations change over time such that a first set of activity regulations applicable at a first time differs from a second set applicable at a second time. At least one of boundaries or restrictions associated with the geo-fence may change over time. The geo-fence may comprise a dynamic indicator that changes over time to reflect changes in the activity regulations. The activity regulations may change periodically, in accordance with a pre-set schedule, or in response to a detected event or condition.

Abstract: A semiconductor structure includes a first active region, a second active region and a dielectric wall. The second active region is disposed adjacent to the first active region, wherein there is a space between the first active region and the second active region. The dielectric wall is formed within the space between the first active region and the second active region. The dielectric wall has a first wall width and a second wall width different from the first wall width.

Abstract: The subject matter described herein is directed to compounds of Formula A; and pharmaceutically acceptable salts thereof, and compositions thereof, including pharmaceutical compositions, and methods of treating disorders associated with TAM receptor tyrosine kinases and/or TYRO3.

Abstract: Disclosed is a method for image processing. The method includes: obtaining one or more image sequences, each of the one or more image sequences including one or more images; determining key information of at least a portion of the one or more images in each of the one or more image sequences; and processing the one or more image sequences based on feature information of each of the one or more image sequences, the feature information of each of the one or more image sequences including the key information of the at least a portion of the one or more images in the image sequence.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region and longitudinally oriented along a first direction and a second well region adjoining the first well region in a second direction. The semiconductor structure also includes a dielectric wall structure formed over a boundary between the first well region and the second well region and first channel structures vertically suspended over a first region of the first well region and laterally attached to a first sidewall surface of the dielectric wall structure. The semiconductor structure includes a first gate structure wrapping around the first channel structures and second channel structures vertically suspended over a second region of the first well region and a second gate structure wrapping around the second channel structures. In addition, the first channel structures is smaller than the second channel structures.

Abstract: Methods, systems, and apparatuses, including computer programs encoded on computer storage media, for performing operations represented by a neural network, The operations comprise: processing a layer input to a network layer of a neural network and one or more nodal weights of the network layer using one or more compute nodes, where at least one of the one or more compute nodes natively generates output having a first data size. The processing comprises processing at least a plurality of upper bits of the layer input to generate an intermediate output. The processing further comprises processing the intermediate output using a new network layer that immediately succeeds the network layer to generate a layer output. The layer output has a higher precision than an output directly generated by processing the layer input via the network layer using the one or more nodes.

Abstract: A semiconductor structure includes first standard cells having first active regions formed over first alternating n-type and p-type wells, the first active regions and the first alternating n-type and p-type wells each extends lengthwise along a first direction, each of the first standard cells includes a first n-type well and a first p-type well; and second standard cells adjacent to the first standard cells, the second standard cells having second active regions formed over second alternating n-type and p-type wells, the second active regions and the second alternating n-type and p-type wells each extends lengthwise along the first direction, each of the second standard cells includes a second n-type well and a second p-type well. The first standard cells have a first cell height, the second standard cells have a second cell height, and the second cell height is greater than the first cell height.

Abstract: An exemplary method includes receiving a device layout for a standard cell that includes a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, signal lines, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal lines and a drain of the transistor. The method includes modifying the device layout for the standard cell. For example, if performance of the standard cell is sensitive to power-related features, the method includes enlarging the power line and the source contact and shrinking the signal lines and the drain contact. If performance of the standard cell is sensitive to signal-related features, the method includes shrinking the power line and the source contact and enlarging the signal lines and the drain contact. A cell height of the standard cell is the same after modifying the device layout.

Abstract: Provided are a flexible molecularly imprinted sensor for in-situ and in-vivo detection of gamma-aminobutyric acid content in plants, and a preparation method and a detection method thereof. The flexible molecularly imprinted sensor includes: a flexible substrate and a graphene electrode unit, the graphene electrode unit being arranged on the flexible substrate, where the graphene electrode unit includes a conductive track, a working electrode, a counter electrode, and a reference electrode, where the counter electrode and the reference electrode are respectively located on two sides of the working electrode, and the working electrode is successively provided from inside to outside with a first modification layer, a second modification layer, and a third modification layer, the first modification layer including an AuNPs material, the second modification layer including an Fc-Ni3(HITP)2-ZnFe-LDH material, and the third modification layer including a molecularly imprinted polymer (MIP) material.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region, a second well region, a third well region, and a fourth well region. The semiconductor structure includes a dielectric wall structure formed over a boundary of the first well region and the second well region and longitudinally oriented along a first direction and first channel structures, second channel structures, third channel structures, and fourth channel structures vertically suspended. In addition, the first channel structures are attached to a first sidewall surface of the dielectric wall structure, and the second channel structures are attached to a second sidewall surface of the dielectric wall structure. Furthermore, the second channel structures have a second width in the second direction, the third channel structures have a third width in the second direction, and the second width is greater than the third width.

Abstract: A system for controlling a vehicle, including one or more communication modules and one or more processors operably coupled to the communication modules. The one or more processors are configured to individually or collectively: receive a geo-fence identifier associated with geo-fence information, where the geo-fence identifier uniquely identifies the geo-fence from other geo-fences; obtain one or more activity regulations for the vehicle based on the geo-fence identifier; and control operation of the vehicle according to the one or more activity regulations.

Abstract: A semiconductor structure includes a substrate, a gate pattern structure, source/drain contacts on opposite sides of the gate pattern structure, a first via and a second via extending through the substrate and in contact with the source/drain contacts, respectively, a gate-cut isolation structure cutting the gate pattern structure. The gate-cut isolation structure extends to a position laterally between the first via and the second via.

Abstract: A method for manufacturing a semiconductor structure includes forming a first fin and a second fin extending in a first direction. Each of the first and second fins includes first semiconductor layers and second semiconductor layers alternating stacked. The method further includes forming an isolation feature between the first and second fins in a second direction perpendicular to the first direction, forming a dummy gate structure over the first fin, the second fin, and the isolation feature, forming an interlayer dielectric layer on opposite sides of the dummy gate structure in the first direction, replacing the dummy gate structure and the first semiconductor layers with a gate structure, replacing the gate structure with a first dielectric structure, forming source/drain contacts on opposite sides of the first dielectric structure in the first direction, and forming a feed-through via under and in contact with the source/drain contacts.

Abstract: A method includes forming a plurality of first semiconductor channel layers stacked in a vertical direction over a substrate; forming a first gate strip surrounding each of the first semiconductor channel layers; forming a plurality of first source/drain regions on either side of each of the first semiconductor channel layers; forming a front-side source/drain contact over a front-side of a first one of the first source/drain regions; forming a first back-side source/drain contact over a back-side of a second one of the first source/drain regions, wherein a front-side of the second one of the first source/drain regions is free of a metal contact; forming a signal line over the front-side source/drain contact; forming a power supply voltage line over the first back-side source/drain contact.

Abstract: Disclosed herein are heterocyclic compounds that activate GLP-1R pathways. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the GLP-1R agonists are disclosed, alone or in combination with other therapeutic agents, for the treatment of diabetes, obesity, and other diseases or conditions dependent on GLP-1R pathways.

Abstract: A wheat leaf rust resistance protein, its encoding gene, and the use thereof are provided. The wheat leaf rust resistance protein includes any of the following (a)-(c): (a) a protein, which consists of the amino acid sequence represented by SEQ ID NO: 3; or (b) a protein, which has an amino acid sequence obtained after the amino acid sequence of the protein (a) undergoes substitution and/or deletion and/or addition of one or more amino acids and which has anti-wheat-leaf-rust activity; or (c) a protein, which has 80% or more identity with the amino acid sequence defined in any of (a) and (b) and which has the same function.

Abstract: A method of forming a semiconductor structure includes a number of operations. Source/drain regions are formed on opposite sides of channel regions over a substrate. A gate structure is formed over the channel regions. A plurality of metal line is formed over a front-side of the substrate. A plurality of metallization layers is formed on a backside of the substrate. A backside source/drain contact is formed on a second one of the source/drain regions, wherein the second one of the source/drain regions is free of the front-side source/drain contact.

Abstract: A semiconductor structure includes a substrate. The substrate includes a shielding region and a device region. The shielding region includes a first active region parallel to a first direction. The device region includes a second active region parallel to the first direction. The semiconductor structure also includes first isolation structures located on the shielding region. The first isolation structures run through the first active region along the second direction. The semiconductor structure also includes first gate structures located on the device region. The first gate structures cross the second active region along the second direction. The semiconductor structure also includes a second isolation structure located on the device region. The second isolation structure runs through the second active region along the second direction. The semiconductor structure also includes a dielectric layer on the substrate and an inductance coil on the dielectric layer.