Patents by Inventor Xiaodong Wang

Xiaodong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015130
    Abstract: A semiconductor structure is provided. A logic cell includes first and second nanostructure transistors. The first nanostructure transistor is formed in a first active region over a first well region having a first conductivity type. The second nanostructure transistor is formed in a second active region over a second well region having a second conductivity type. The first and second nanostructure transistors share a gate structure. First and second source/drain features of the first nanostructure transistor are formed in the first active region. Third and fourth source/drain features of the second nanostructure transistor are formed in a first portion and a second portion of the second active region, respectively. A first distance between the first active region and the first portion of the second active region is different from a second distance between the first active region and the second portion of the second active region.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Yu-Lung TUNG, Xiaodong WANG, Jhon-Jhy LIAW
  • Publication number: 20250006558
    Abstract: A method includes forming first, second, third, fourth, fifth, and sixth channel patterns on a semiconductor substrate; forming a first isolation wall interposing the first and second channel patterns, a second isolation wall interposing the third and fourth channel patterns, wherein the first isolation wall further continuously extends to interpose the fifth and sixth channel patterns; forming a first gate pattern extending across the first, second, third, and fourth channel patterns and the first and second isolation walls, and a second gate pattern extending across the fifth and sixth channel patterns and the first isolation wall from the top view, wherein the first, second, third, fourth, and sixth channel patterns respectively have first, second, third, fourth, and sixth dimensions in a lengthwise direction of the first gate pattern, and the sixth dimension is greater than the first, second, third, and fourth dimensions.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lung TUNG, Xiaodong Wang, Jhon Jhy Liaw
  • Publication number: 20240416460
    Abstract: The present disclosure provides a protective method and system combining process monitoring and control in laser drilling. This method includes collecting signal evolution information, a current hole depth, and motion track information in a laser drilling process; performing a feature extraction on the signal to obtain sequential eigenvalues evolving over time, and constructing a prediction model of the penetration time based on the eigenvalues; combining the hole depth and motion track information with the eigenvalues to construct a drilling stage identification model; combining a prediction result of the prediction model of penetration time and identification confidence of the identification model at different moments to construct a state identification model; and judging a current drilling stage according to the model, controlling the processing process according to a judgment result, and using different drilling strategies at different drilling stages.
    Type: Application
    Filed: August 29, 2024
    Publication date: December 19, 2024
    Applicant: XI'AN JIAOTONG UNIVERSITY
    Inventors: Xuesong MEI, Tao SUN, Wanqin ZHAO, Zhengjie FAN, Jianlei CUI, Wenjun WANG, Bin LIU, Wenqiang DUAN, Xiaodong WANG, Aifei PAN
  • Publication number: 20240420947
    Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Shiyu YUE, Jiajie CEN, Sahil Jaykumar PATEL, Zhimin QI, Ju Hyun OH, Aixi ZHANG, Xingyao GAO, Wei LEI, Yi XU, Yu LEI, Tsung-Han YANG, Xiaodong WANG, Xiangjin XIE, Yixiong YANG, Kevin KASHEFI, Rongjun WANG
  • Patent number: 12168648
    Abstract: Provided herein are opioid receptor modulators and pharmaceutical compositions comprising said compounds.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: December 17, 2024
    Assignee: EPIODYNE, INC.
    Inventors: Julio Cesar Medina, Alok Nerurkar, Corinne Sadlowski, Frederick Seidl, Heng Cheng, Jason Duquette, John Lee, Martin Holan, Pingyu Ding, Xiaodong Wang, Tien Widjaja, Thomas Nguyen, Ulhas Bhatt, Yihong Li, Zhi-liang Wei
  • Publication number: 20240409558
    Abstract: Disclosed herein are heterocyclic compounds that inhibit the binding of KRas. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the KRas inhibitors are disclosed, alone or in combination with other therapeutic agents, for the treatment of autoimmune diseases or conditions, heteroimmune diseases or conditions, cancer, including lymphoma, leukemia, lung cancer, colorectal cancer, pancreatic cancer, and other diseases or conditions dependent on KRas interaction.
    Type: Application
    Filed: September 12, 2022
    Publication date: December 12, 2024
    Inventors: Yongli Su, Thu Phan, Thomas Butler, James T. Palmer, Solomon Ungashe, Ravindra B. Upassani, Neil Howard Squires, David Sperandio, Thorsten A. Kirschberg, Xiaodong Wang, Brian Law, Nan-Horng Lin
  • Publication number: 20240412642
    Abstract: An aerial vehicle includes a communication unit configured to receive a wireless signal from a geo-fencing device, and a flight controller configured to generate one or more control signals that cause the aerial vehicle to operate in accordance with a set of flight regulations generated based on the wireless signal. The geo-fencing device is configured not for landing of the aerial vehicle. The set of flight regulations includes rules for controlling at least one of the aerial vehicle, a carrier carried by the aerial vehicle, or a payload of the aerial vehicle.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Inventors: Ming GONG, Jin DAI, Hao CUI, Xiaodong WANG, Han HUANG, Jun WU, Wei FAN, Ning MA, Xinhua RONG, Xingsen LIN
  • Publication number: 20240387632
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region, a second well region, a third well region, and a fourth well region. The semiconductor structure includes a dielectric wall structure formed over a boundary of the first well region and the second well region and longitudinally oriented along a first direction and first channel structures, second channel structures, third channel structures, and fourth channel structures vertically suspended. In addition, the first channel structures are attached to a first sidewall surface of the dielectric wall structure, and the second channel structures are attached to a second sidewall surface of the dielectric wall structure. Furthermore, the second channel structures have a second width in the second direction, the third channel structures have a third width in the second direction, and the second width is greater than the third width.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lung TUNG, Xiaodong WANG, Jhon-Jhy LIAW
  • Publication number: 20240383882
    Abstract: The present invention discloses a number of polycyclic amines that are useful as opioid receptor modulators. The compounds of the invention are useful in both therapeutic and diagnostic methods, including for treating pain, neurological disorders, cardiac disorders, bowel disorders, drug and alcohol addiction, drug overdose, urinary disorders, respiratory disorders, sexual dysfunction, psoriasis, graft rejection or cancer.
    Type: Application
    Filed: January 30, 2024
    Publication date: November 21, 2024
    Inventor: XIAODONG WANG
  • Patent number: 12142032
    Abstract: An embodiment of a semiconductor package apparatus may include technology to pre-process an image to simplify a background of the image, and perform object detection on the pre-processed image with the simplified background. For example, an embodiment of a semiconductor package may include technology to pre-process an image to subtract the background from the image and perform object detection on the pre-processed image with the background subtracted. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Yuming Li, Zhen Zhou, Xiaodong Wang, Quan Yin
  • Publication number: 20240355877
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first well region and longitudinally oriented along a first direction and a second well region adjoining the first well region in a second direction. The semiconductor structure also includes a dielectric wall structure formed over a boundary between the first well region and the second well region and first channel structures vertically suspended over a first region of the first well region and laterally attached to a first sidewall surface of the dielectric wall structure. The semiconductor structure includes a first gate structure wrapping around the first channel structures and second channel structures vertically suspended over a second region of the first well region and a second gate structure wrapping around the second channel structures. In addition, the first channel structures is smaller than the second channel structures.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Yu-Lung TUNG, Xiaodong WANG, Jhon-Jhy LIAW
  • Publication number: 20240321958
    Abstract: In an embodiment, a method includes: placing a first cell in a device layout, the first cell defining a first transistor, the first transistor including a first quantity of first nanostructures; placing a second cell in the device layout directly adjacent to the first cell, the second cell defining a second transistor, the second transistor including a second quantity of second nanostructures, the second quantity being different than the first quantity; generating a lithography mask based on the device layout; and manufacturing a semiconductor device using the lithography mask.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Yu-Lung Tung, Xiaodong Wang, Jhon Jhy Liaw
  • Publication number: 20240312988
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a hybrid unit cell. The hybrid unit cell includes at least one first sub-cell having a first cell height and at least one second sub-cell having a second cell height. The first sub-cell includes a plurality of first gate-all-around (GAA) nanosheet transistors. The second sub-cell includes a plurality of second GAA nanosheet transistors. The first cell height is higher than the second cell height, and the first GAA nanosheet transistor has a wider nanosheet width than the second GAA nanosheet transistor.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lung TUNG, Xiaodong WANG, Jhon-Jhy LIAW
  • Patent number: 12094699
    Abstract: Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the substrate support; a first magnet disposed about the body proximate the collimator; a second magnet disposed about the body above the support surface and entirely below the collimator and spaced vertically below the first magnet; and a third magnet disposed about the body and spaced vertically between the first magnet and the second magnet. The first, second, and third magnets are configured to generate respective magnetic fields to redistribute ions over the substrate.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: September 17, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiaodong Wang, Joung Joo Lee, Fuhong Zhang, Martin Lee Riker, Keith A. Miller, William Fruchterman, Rongjun Wang, Adolph Miller Allen, Shouyin Zhang, Xianmin Tang
  • Patent number: 12095885
    Abstract: A method for removing stale context in a service instance, comprising: generating a user message according to UID and request instruction of received request data; routing the user message to first service instance; if target context corresponding to the user ID is saved in a global cache of a database, loading the target context from the global cache; when the loaded target context does not belong to the first service instance, setting the loaded target context to belong to the first service instance, wherein the set target context is saved into a first local cache and the global cache; and instructing to remove one or more invalid target contexts corresponding to the user ID from one or more other service instances, wherein the invalid target contexts are target contexts which do not belong to the first service instance, such that stale contexts which are the invalid target context are removed.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: September 17, 2024
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Xiaodong Wang, Qinghua Liao
  • Publication number: 20240300892
    Abstract: The present invention provides MDM2 inhibitor compounds of Formula I, wherein the variables are defined above, which compounds are useful as therapeutic agents, particularly for the treatment of cancers. The present invention also relates to pharmaceutical compositions that contain an MDM2 inhibitor.
    Type: Application
    Filed: October 11, 2023
    Publication date: September 12, 2024
    Inventors: Michael D. Bartberger, Ana Gonzalez Buenrostro, Hilary Plake Beck, Xiaoqi Chen, Richard Victor Connors, Jeffrey Deignan, Jason A. Duquette, I, John Eksterowicz, Benjamin Fisher, Brian M. Fox, Jiasheng Fu, Zice Fu, Felix Gonzalez Lopez De Turiso, Michael W. Gribble, Darin J. Gustin, Julie A. Heath, Xin Huang, XianYun Jiao, Michael G. Johnson, Frank Kayser, David John Kopecky, SuJen Lai, Yihong Li, Zhihong Li, Jiwen Liu, Jonathan D. Low, Brian S. Lucas, Zhihua MA, Lawrence R. McGee, Joel McIntosh, Dustin L. McMinn, Julio C. Medina, Jeffrey Thomas Mihalic, Steven H. Olson, Yossup Rew, Philip M. Roveto, Daqing Sun, Xiaodong Wang, Yingcai Wang, Xuelei Yan, Ming Yu, Jiang Zhu
  • Publication number: 20240299223
    Abstract: Embodiments of the present disclosure provide a collapsible wheelchair, including: a movable chassis; a chair; a chair backrest; at least one first folding mechanism, installed between the movable chassis and the chair; and at least one second folding mechanism, connected between the chair and the chair backrest; where, the at least one first folding mechanism and the at least one second folding mechanism are connected in series and both have a four-rod linkage structure, and when the collapsible wheelchair is switched from a folded state to an open state or from the open state to the folded state, the at least one first folding mechanism and the at least one second folding mechanism are configured to move simultaneously. The collapsible wheelchair provided by the present disclosure is convenient in terms of the operation and easy to operate.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Inventors: Jianguo LI, Yongqiang LI, Jie LIU, Xiaodong WANG, Zhefu ZHANG, Canfeng LIU, Xiangcheng LIAO
  • Patent number: D1044202
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 1, 2024
    Inventor: Xiaodong Wang
  • Patent number: D1045693
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: October 8, 2024
    Inventors: Jianguo Li, Xianyu Su, Jie Liu, Xiaodong Wang, Hengjie Tang
  • Patent number: D1049943
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: November 5, 2024
    Assignee: Jiangsu Bangbang Intelligent Technology Co., Ltd.
    Inventors: Jianguo Li, Zhefu Zhang, Jie Liu, Xiaodong Wang, Yongqiang Li