Abstract: Provided are a 3D filter circuit and a 3D filter. The 3D filter circuit includes a multilayer structure. The multilayer structure includes at least two conductive layers and at least one organic dielectric layer. Each organic dielectric layer is disposed between different conductive layers. The multilayer structure is configured to form at least one capacitor.

Abstract: A semiconductor structure includes a substrate. The substrate includes a shielding region and a device region. The shielding region includes a first active region parallel to a first direction. The device region includes a second active region parallel to the first direction. The semiconductor structure also includes first isolation structures located on the shielding region. The first isolation structures run through the first active region along the second direction. The semiconductor structure also includes first gate structures located on the device region. The first gate structures cross the second active region along the second direction. The semiconductor structure also includes a second isolation structure located on the device region. The second isolation structure runs through the second active region along the second direction. The semiconductor structure also includes a dielectric layer on the substrate and an inductance coil on the dielectric layer.

Abstract: Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the substrate support; a first magnet disposed about the body proximate the collimator; a second magnet disposed about the body above the support surface and entirely below the collimator and spaced vertically below the first magnet; and a third magnet disposed about the body and spaced vertically between the first magnet and the second magnet. The first, second, and third magnets are configured to generate respective magnetic fields to redistribute ions over the substrate.

Abstract: A semiconductor structure includes a substrate, a bottom metal structure located on the substrate, a first dielectric layer located on the bottom metal structure, first plug structures, second plug structures, and first metal structures. The substrate includes a base, a device structure located on the base, and conductive layers located on the device structure. The bottom metal structure is electrically connected to the conductive layers. The first dielectric layer includes a first opening structure and a second opening structure. The first opening structure includes first grooves and second grooves on top of the first grooves, and the second opening structure includes third grooves and fourth grooves on top of the third grooves. The first plug structures are located in the first grooves, and the second plug structures are located in the third grooves. The first metal structures are located in the second grooves and the fourth grooves.

Abstract: An inductor coil includes: a substrate, including a base, a device layer on the base, a conductive layer, and an electrical interconnect structure; a plurality of stacked coil layers being on the substrate, each of the plurality of stacked coil layers including a plurality of sub-coil structures on a same layer; and a plurality of electrical connection layers between two adjacent coil layers, a projection pattern of each electrical connection layer on a surface of the substrate being within a range of projection patterns of two adjacent coil layers that are in contact with the plurality of electrical connection layers on the surface of the substrate, and all the plurality of coil layers being connected in parallel through all the plurality of electrical connection layers.

Abstract: Disclosed herein are heterocyclic compounds that inhibit the activity of FLT3. Also described are specific covalent inhibitors of FLT3. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the FLT3 inhibitors are disclosed, alone or in combination with other therapeutic agents, for the treatment of proliferative diseases or conditions, including hematological malignancies and other diseases or conditions dependent on FLT3 activity.

Abstract: Embodiments of the present disclosure provide a DC-DC converter, and a DC output device. The DC-DC converter includes: a housing; a detachable connection structure arranged on the housing and configured to detachably connect with a battery module; a DC-DC conversion module received in the housing and configured to convert a direct current input from the battery module to a direct current at a preset voltage; and one or more current output ports arranged on the housing, the one or more current output ports are electrically connected with the DC-DC conversion module and are configured to output the direct current at the preset voltage obtained from the DC-DC conversion module.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a physical vapor deposition processing chamber comprises a chamber body defining a processing volume, a substrate support disposed within the processing volume and comprising a substrate support surface configured to support a substrate, a power supply configured to energize a target for sputtering material toward the substrate, an electromagnet operably coupled to the chamber body and positioned to form electromagnetic filed lines through a sheath above the substrate during sputtering for directing sputtered material toward the substrate, and a controller operably coupled to the physical vapor deposition processing chamber for controlling the electromagnet based on a recipe comprising a pulsing schedule for pulsing the electromagnet during operation to control directionality of ions relative to a feature on the substrate.

Abstract: Embodiments of the present disclosure provide a DC-AC converter, including: a converter housing; an electrical connector, arranged on the converter housing and configured to be electrically connected with the battery module; a DC-AC conversion module arranged in the converter housing and configured to convert a direct current output from the battery module to an alternating current; and a detachable connection structure arranged on the converter housing and configured to detachably connect the DC-AC converter to the battery module. Embodiments of the present disclosure further provide an AC output device, in which the DC-AC converter is detachably connected to the battery module. The DC-AC converter can be detached from the AC output device when the user does not need the current conversion function.

Abstract: Embodiments of the present disclosure relates to the technical field of mobile power supply, and a battery module of a battery-replacement outdoor power supply is provided. The battery module of the battery-replacement outdoor power supply is incorporated into a battery compartment of the battery-replacement outdoor power supply and includes a battery pack, a housing, and a quick connector penetrating through the housing. One end of the quick connector is electrically connected to the battery pack, and the other end of the quick connector is detachably connected to a slot in the battery compartment.

Abstract: This disclosure belongs to the field of communication technologies, and provides a network chip management method and apparatus, a communication device, and a storage medium. According to the network chip management method provided in this disclosure, an idle target network chip is determined based on at least one of a port status, a configuration status, and a traffic status of a network chip; and a first functional module in the target network chip is controlled to run at a sleep running frequency, so that power consumption of the target network chip can be effectively reduced.

Abstract: An exemplary method includes receiving a device layout for a standard cell that includes a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, signal lines, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal lines and a drain of the transistor. The method includes modifying the device layout for the standard cell. For example, if performance of the standard cell is sensitive to power-related features, the method includes enlarging the power line and the source contact and shrinking the signal lines and the drain contact. If performance of the standard cell is sensitive to signal-related features, the method includes shrinking the power line and the source contact and enlarging the signal lines and the drain contact. A cell height of the standard cell is the same after modifying the device layout.

Abstract: Embodiments of the disclosure provide systems and methods for providing random access to segmented and encrypted or compressed data stored in a repository. Retrieving at least a portion of a file stored in a repository can comprise storing a plurality of files in the repository. A request to retrieve at least a portion of one of the plurality of files can be received and object metadata for the requested one of the plurality of files can be obtained. A determination can be made based on the obtained metadata as to whether the requested one of the plurality of files is a multipart file. In response to determining the requested one of the plurality of files is not a multipart file, a single file retrieval process performing and in response to determining the requested one or the plurality of files is a multipart file, a multipart retrieval process can be performed.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer having a functional region and a non-functional region surrounding the functional region; a first dielectric layer formed on the wafer; a first opening formed in the first dielectric layer on the non-function region of the wafer; and a first connection layer formed in the first opening. The first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening.

Abstract: The invention provides compounds that are inhibitors or covalent modifiers of succinate dehydrogenase subunit B (SDHB) and/or inhibitors of apoptosis, and pharmaceutically acceptable salts, hydrates and stereoisomers thereof. The compounds are employed in pharmaceutical compositions, and methods of making and use, including treating a person in need thereof with an effective amount of the compound or composition.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing content. One of the methods includes receiving a target image at an image platform; determining one or more images related to the target image; determining queries associated with the related images; deriving candidate keywords from the determined queries; filtering the candidate keywords to select one or more keywords; and providing the image to one or more users in response to respective incoming queries based on the one or more keywords.

Abstract: Mechanisms for recovering data symbols in multiple-input, multiple-output (MIMO) receivers, the mechanisms comprising receiving, at Na antennas that each have an output: first signals corresponding to Np pilot symbols transmitted from each of K transmitters for a total of Np*K transmitted pilot symbols; and second signals corresponding to a plurality of transmitted data symbols transmitted from the K transmitters, wherein Np is less than Na, and wherein K is less than Na; receiving, at a hardware processor, first digital signals representing the Np*K transmitted pilot symbols; receiving, at the hardware processor, second digital signals representing the plurality of transmitted data symbols; and recovering the plurality of transmitted data symbols using the second digital signals and no more pilot symbols than the Np*K transmitted pilot symbols represented by the first digital signals using the hardware processor.

Abstract: The application discloses a method and system for segmenting a lung image. The method may include obtaining a target image relating to a lung region. The target image may include a plurality of image slices. The method may also include segmenting the lung region from the target image, identifying an airway structure relating to the lung region, and identifying one or more fissures in the lung region. The method may further include determining one or more pulmonary lobes in the lung region.