Patents by Inventor Xiaoju Wu

Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110110160
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 12, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Patent number: 7919368
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: April 5, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef C. Mitros
  • Patent number: 7893768
    Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Zhengyu Wang, Xiaoju Wu
  • Publication number: 20100302854
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Publication number: 20100264466
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: June 29, 2010
    Publication date: October 21, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Publication number: 20100231299
    Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Applicant: Texas Instrument Incorporated
    Inventors: Zhengyu Wang, Xiaoju Wu
  • Patent number: 7785906
    Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Publication number: 20100164004
    Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AMITAVA CHATTERJEE, SEETHARAMAN SRIDHAR, XIAOJU WU, VLADIMIR F. DROBNY
  • Patent number: 7745274
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Patent number: 7687856
    Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: March 30, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Xiaoju Wu
  • Patent number: 7598547
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P Pendharker, Pinghai Hao, Xiaoju Wu
  • Publication number: 20090153174
    Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Patent number: 7457173
    Abstract: An electrically erasable programmable read only memory (EEPROM) (500) is disclosed having improved data retention and read/write endurance. The EEPROM also lacks a more conventional cross coupling arrangement and thus is more area efficient than conventional EEPROM cells. The EEPROM (500) includes a PMOS transistor portion (514a) and an NMOS transistor portion (514b), where respective currents of these devices are compared to one another (e.g., subtracted) to give a differential reading that provides for the state of the EEPROM (500).
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20080283966
    Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.
    Type: Application
    Filed: August 1, 2008
    Publication date: November 20, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Shanjen Pan, Xiaoju Wu, Peter Ying
  • Publication number: 20080277731
    Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Xiaoju Wu
  • Publication number: 20080225593
    Abstract: A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the source-to-floating gate capacitance is substantially greater than the drain-to-floating gate capacitance. The source-to-floating gate capacitance is, for example, at least about three times greater than the drain-to-floating gate capacitance to enable the memory device to be electrically programmed or erased by applying a potential between a source electrode and a drain electrode without using a control gate.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 18, 2008
    Inventors: Jozef Czeslaw Mitros, Xiaoju Wu
  • Publication number: 20080217664
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Patent number: 7402874
    Abstract: The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An inner transistor based cell (130) formed from the inner ring (108) is shielded from isolation material (106) by one or more outer rings (110). The lack of overlap between the inner transistor and any isolation material promotes enhanced charge/data retention by mitigating high electric fields that may develop at such overlap regions (30, 32).
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: July 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Patent number: 7348228
    Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Patent number: 7307309
    Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: December 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Jozef Mitros, Xiaoju Wu