Patents by Inventor Xiaoju Wu
Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150294967Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 9099523Abstract: A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the buried layer. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the buried layer.Type: GrantFiled: November 2, 2012Date of Patent: August 4, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 8859791Abstract: A process for producing an alkylene oxide by olefin epoxidation, wherein said process comprises the steps of: (1) in a first olefin epoxidation condition, in the presence of a first solid catalyst, a first mixed stream containing a solvent, an olefin and H2O2 is subjected to an epoxidation in one or more fixed bed reactors and/or one or more moving bed reactors until the conversion of H2O2 reaches 50%-95%, then, optionally, the resulting reaction mixture obtained in the step (1) is subjected to a separation to obtain a first stream free of H2O2 and a second stream containing the unreacted H2O2, and the olefin is introduced to the second stream to produce a second mixed stream, or optionally, the olefin is introduced to the reaction mixture obtained in the step (1) to produce a second mixed stream; (2) in a second olefin epoxidation condition, the reaction mixture obtained in the step (1) or the second mixed stream obtained in the step (1) and a second solid catalyst are introduced to one or more slurry bed reType: GrantFiled: October 11, 2011Date of Patent: October 14, 2014Assignees: China Petroleum & Chemical Corporation, Hunan Changling Petrochemical Science and Technology Development Co. Ltd., Research Institute of Petroleum Processing, SinopecInventors: Hua Li, Min Lin, Xiaoju Wu, Wei Wang, Chijian He, Jizao Gao, Xingtian Shu, Shuanghua Wan, Bin Zhu
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Publication number: 20140124828Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 8581324Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: GrantFiled: December 6, 2011Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Publication number: 20130253208Abstract: The present invention provides a catalyst and the preparation process thereof and a process of epoxidising olefin using the catalyst. The catalyst contains a binder and a titanium silicate, the binder being an amorphous silica, the titanium silicate having a MFI structure, and the crystal grain of the titanium silicate having a hollow structure, with a radial length of 5-300 nm for the cavity portion of the hollow structure, wherein the adsorption capacity of benzene measured for the titanium silicate under the conditions of 25 degrees C., P/P0=0.Type: ApplicationFiled: October 11, 2011Publication date: September 26, 2013Applicants: CHINA PETROLEUM & CHEMICAL CORPORATION, Research Institute of Petroleum Processing, Sinope Sinopec, Hunan Changling Pertrochemical Science and Technology Development Co. Ltd.Inventors: Min Lin, Hua Li, Wei Wang, Chijian He, Xiaoju Wu, Jizao Gao, Xichun She, Jun Long, Qingling Chen
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Publication number: 20130211112Abstract: A process for producing an alkylene oxide by olefin epoxidation, wherein said process comprises the steps of: (1) in a first olefin epoxidation condition, in the presence of a first solid catalyst, a first mixed stream containing a solvent, an olefin and H2O2 is subjected to an epoxidation in one or more fixed bed reactors and/or one or more moving bed reactors until the conversion of H2O2 reaches 50%-95%, then, optionally, the resulting reaction mixture obtained in the step (1) is subjected to a separation to obtain a first stream free of H2O2 and a second stream containing the unreacted H2O2, and the olefin is introduced to the second stream to produce a second mixed stream, or optionally, the olefin is introduced to the reaction mixture obtained in the step (1) to produce a second mixed stream; (2) in a second olefin epoxidation condition, the reaction mixture obtained in the step (1) or the second mixed stream obtained in the step (1) and a second solid catalyst are introduced to one or more slurry bed reType: ApplicationFiled: October 11, 2011Publication date: August 15, 2013Applicant: CHINA PETROLEUM & CHEMICAL CORPORATIONInventors: Hua Li, Min Lin, Xiaoju Wu, Wei Wang, Chijian He, Jizao Gao, Xingtian Shu, Shuanghua Wan, Bin Zhu
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Publication number: 20120074479Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Patent number: 8125830Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: GrantFiled: January 11, 2011Date of Patent: February 28, 2012Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Patent number: 8114744Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.Type: GrantFiled: December 29, 2008Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Seetharaman Sridhar, Xiaoju Wu, Vladimir F. Drobny
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Patent number: 8067795Abstract: A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the source-to-floating gate capacitance is substantially greater than the drain-to-floating gate capacitance. The source-to-floating gate capacitance is, for example, at least about three times greater than the drain-to-floating gate capacitance to enable the memory device to be electrically programmed or erased by applying a potential between a source electrode and a drain electrode without using a control gate.Type: GrantFiled: March 12, 2007Date of Patent: November 29, 2011Assignee: Texas Instruments IncorporatedInventors: Jozef Czeslaw Mitros, Xiaoju Wu
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Publication number: 20110110160Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: ApplicationFiled: January 11, 2011Publication date: May 12, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Patent number: 7919368Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: GrantFiled: May 29, 2009Date of Patent: April 5, 2011Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Jozef C. Mitros
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Patent number: 7893768Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.Type: GrantFiled: March 10, 2009Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Zhengyu Wang, Xiaoju Wu
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Publication number: 20100302854Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.Type: ApplicationFiled: May 29, 2009Publication date: December 2, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Publication number: 20100264466Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
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Publication number: 20100231299Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.Type: ApplicationFiled: March 10, 2009Publication date: September 16, 2010Applicant: Texas Instrument IncorporatedInventors: Zhengyu Wang, Xiaoju Wu
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Patent number: 7785906Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.Type: GrantFiled: December 12, 2007Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Jozef Czeslaw Mitros
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Publication number: 20100164004Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: AMITAVA CHATTERJEE, SEETHARAMAN SRIDHAR, XIAOJU WU, VLADIMIR F. DROBNY
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Patent number: 7745274Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.Type: GrantFiled: March 8, 2007Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao