Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract: Systems and methods for predicting content performance with interest data include receiving a content selection request that includes a client identifier. One or more topical interest categories associated with the client identifier may be used as inputs to a prediction model to predict the likelihood of an online action occurring as a result of third-party content being selected. The predicted likelihood may be used to select third-party content.

Abstract: A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Abstract: Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.

Abstract: Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.

Abstract: Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.

Abstract: Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.

Abstract: A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at least one die of a wafer and includes at least one racing path circuit having at least two paths. The method further includes collecting the race condition testing data and evaluating the collected race condition testing data. The race condition testing data is correlated to a process variation of the at least one die.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength. On-chip clock distribution is an important application where cell libraries of the invention can provide significant advantages.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength.

Abstract: A standard cell library having a globally scalable transistor channel length is provided. In this library, the channel length of every transistor within a cell can be globally scaled, within a predetermined range, without changing cell functionality, cell size, or cell terminal positions. Such a cell library advantageously addresses the intra-generational redesign problem, since cell channel lengths in library cells can be decreased as fabrication technology evolves, without requiring intra-generational redesign of existing circuit layouts. Preferably, this change in channel length is obtained by altering a single mask layer of the library design (e.g., the mask for the poly-silicon layer).

Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength. On-chip clock distribution is an important application where cell libraries of the invention can provide significant advantages.

Abstract: A standard cell library having a globally scalable transistor channel length is provided. In this library, the channel length of every transistor within a cell can be globally scaled, within a predetermined range, without changing cell functionality, cell size, or cell terminal positions. Such a cell library advantageously addresses the intra-generational redesign problem, since cell channel lengths in library cells can be decreased as fabrication technology evolves, without requiring intra-generational redesign of existing circuit layouts. Preferably, this change in channel length is obtained by altering a single mask layer of the library design (e.g., the mask for the poly-silicon layer).