Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

Abstract: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

Abstract: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional cell libraries typically have drive strengths which correspond to a predetermined set of cell physical areas. Preferably, the spacing between adjacent design delays is a non-decreasing function of cell drive strength. Such spacing reduces quantization induced over-design compared to conventional cell libraries which have a design delay spacing that is a decreasing function of cell drive strength.

Abstract: The invention provides a method and system for reducing capacitive coupling for transmission lines. Where there is a plurality of parallel transmission lines, a first half of the transmission lines (every second one) are inverted at their driving points, and are reinverted at a half-way point between their driving points and their receiving points, using an inverter placed halfway along the transmission line. A second half of the transmission lines are inverted at the half-way point, and are reinverted at their receiving points. Thereby, every second one of multiple transmission lines is inverted at any point in the transmission line, causing capacitive coupling to self-cancel across the entire transmission line, reducing crosstalk and speeding rise time.

Abstract: A speed-up circuit is employed in a semiconductor chip of the type that includes a P-type substrate with a plurality of NPN transistors integrated into a surface thereof. Those transistors include a first NPN transistor having a base which receives a control signal, a collector coupled to a voltage bus, and an emitter which drives a first resistor plus a base of a second NPN transistor plus a small parasitic capacitance. The second NPN transistor has a collector coupled to a voltage bus, and an emitter which drives a second resistor plus a larger parasitic capacitance. And, the speed-up circuit is comprised of: a PNP transistor having an emitter coupled to the large capacitance, a base coupled to a tap on the first resistor, and a collector coupled to the substrate.

Abstract: An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.

Abstract: An integrated circuit chip having improved static discharge protection comprises a semiconductor substrate with a major surface, a plurality of transistors that are integrated into the surface, patterned conductors that interconnect the transistors and route input signals to the transistors, with the patterned conductors including metal pads for receiving the input signals from an external source; wherein the improvement comprises respective diodes which are integrated into the surface directly beneath the metal pads, and which connect the pads to the substrate and conduct electrostatic charge therebetween. With this structure, no additional chip space is required over that which is used by the transistors which are being protected since the diodes are hidden in the normally unused chip space beneath the pads.