Patents by Inventor Xinhai Han

Xinhai Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12195846
    Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 14, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Xinhai Han, Hang Yu, Kesong Hu, Kristopher R. Enslow, Masaki Ogata, Wenjiao Wang, Chuan Ying Wang, Chuanxi Yang, Joshua Maher, Phaik Lynn Leong, Grace Qi En Teong, Alok Jain, Nagarajan Rajagopalan, Deenesh Padhi, SeoYoung Lee
  • Publication number: 20240427979
    Abstract: A method includes obtaining, by a processing device, first data indicative of overlay error of a substrate. The method further includes generating second data indicative of first stress uniformity of the substrate based on the first data. The method further includes performing a corrective action based on the second data.
    Type: Application
    Filed: June 24, 2024
    Publication date: December 26, 2024
    Inventors: Zhiling Dun, Allison Yao, Jingmin Leng, Xinhai Han, Deenesh Padhi
  • Patent number: 12110590
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: October 8, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Gregory Eugene Chichkanoff, Xinhai Han, Masaki Ogata, Kristopher Enslow, Wenjiao Wang
  • Publication number: 20240332006
    Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor to the processing region. The methods may include generating plasma effluents of the silicon-containing precursor and plasma effluents of the hydrogen-containing precursor in the processing region. The plasma effluents may be generated at a frequency greater than 15 MHz. The methods may include depositing a silicon-containing material on the substrate.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tianyang Li, Jisung Park, Xinhai Han, Woongsik Nam, Deenesh Padhi
  • Publication number: 20240288838
    Abstract: A method includes identifying a material associated with a substrate processing operation of a recipe. The method further includes determining an expected total residual thickness value subsequent to the substrate processing operation. The method further includes determining, based on the expected total residual thickness value, an expected material thickness value of the material associated with the substrate processing operation. The method further includes updating the recipe based on the material and the expected material thickness value of the material to generate an updated recipe. The method further includes causing a substrate to be processed based on the updated recipe.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 29, 2024
    Inventors: Albert Liu, Mitesh Harshad Sanghvi, Venkatanarayana Shankaramurthy, Yulian Yao, Xinhai Han
  • Publication number: 20240243018
    Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first data set reflecting distortions associated with a substrate and generating a second data set reflecting reduced noise in the distortions of the first data set. A third data set is generated by projecting a plurality of direction components associated with the second data set to a radial direction and a stress or strain map is generated indicating at least one of stress or strain exhibited by the substrate by determining a magnitude associated with a subset of the third data set.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 18, 2024
    Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
  • Patent number: 11948846
    Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
  • Patent number: 11946140
    Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Anantha K. Subramani, Seyyed Abdolreza Fazeli, Yang Guo, Ramcharan Sundar, Arun Kumar Kotrappa, Steven Mosbrucker, Steven D. Marcus, Xinhai Han, Kesong Hu, Tianyang Li, Philip A. Kraus
  • Patent number: 11898249
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Wenyoung Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward W. Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik, Ganesh Balasubramanian
  • Publication number: 20240044000
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Inventors: Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Daemian Raj BENJAMIN RAJ, Amit Kumar BANSAL, Juan Carlos ROCHA-ALVAREZ, Gregory Eugene CHICHKANOFF, Xinhai HAN, Masaki OGATA, Kristopher ENSLOW, Wenjiao WANG
  • Publication number: 20240045399
    Abstract: A method includes receiving time trace sensor data associated with a substrate processing procedure. The substrate processing procedure includes two or more sets of processing conditions. At least a first set of processing conditions and a second set of processing conditions each include one or more operations performed repeatedly. The method further includes separating a first and second portion of the time trace sensor data corresponding to the first and second sets of processing conditions into a first and second plurality of cycle data. The method further includes processing the first plurality of cycle data and the second plurality of cycle data to generate summary data. The method further includes providing an alert to a user. The alert is based on the summary data.
    Type: Application
    Filed: May 17, 2022
    Publication date: February 8, 2024
    Inventors: Qinglin Chai, Yue Ma, Liming Zhang, Xinhai Han, Chuan Ying Wang
  • Patent number: 11851759
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: December 26, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Gregory Eugene Chichkanoff, Xinhai Han, Masaki Ogata, Kristopher Enslow, Wenjiao Wang
  • Patent number: 11837448
    Abstract: Examples disclosed herein relate to a method and apparatus for cleaning and repairing a substrate support having a heater disposed therein. A method includes (a) cleaning a surface of a substrate support having a bulk layer, the substrate support is disposed in a processing environment configured to process substrates. The cleaning process includes forming a plasma at a high temperature from a cleaning gas mixture having a fluorine containing gas and oxygen. The method includes (b) removing oxygen radicals from the processing environment with a treatment plasma formed from a treatment gas mixture. The treatment gas mixture includes the fluorine containing gas. The method further includes (c) repairing an interface of the substrate support and the bulk layer with a post-treatment plasma. The post-treatment plasma is formed from a post-treatment gas mixture including a nitrogen containing gas. The high temperature is greater than or equal to about 500 degrees Celsius.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: December 5, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Shuran Sheng, Lin Zhang, Jiyong Huang, Jang Seok Oh, Joseph C. Werner, Nitin Khurana, Ganesh Balasubramanian, Jennifer Y. Sun, Xinhai Han, Zhijun Jiang
  • Publication number: 20230359179
    Abstract: An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventors: Mitesh Sanghvi, Venkatanarayana Shankarmurthy, Yulian Yao, Chuan Ying Wang, Xinhai Han
  • Patent number: 11776835
    Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 3, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Zheng John Ye, Daemian Raj Benjamin Raj, Rana Howlader, Abhigyan Keshri, Sanjay G. Kamath, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Shailendra Srivastava, Kristopher R. Enslow, Xinhai Han, Deenesh Padhi, Edward P. Hammond
  • Publication number: 20230238289
    Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.
    Type: Application
    Filed: April 4, 2023
    Publication date: July 27, 2023
    Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
  • Publication number: 20230193466
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Michael Wenyoung TSIANG, Masaki OGATA, Zhijun JIANG, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Jianhua ZHOU, Ramprakash SANKARAKRISHNAN, Amit Kumar BANSAL, Jeongmin LEE, Todd EGAN, Edward W. BUDIARTO, Dmitriy PANASYUK, Terrance Y. LEE, Jian J. CHEN, Mohamad A. AYOUB, Heung Lak PARK, Patrick REILLY, Shahid SHAIKH, Bok Hoen KIM, Sergey STARIK, Ganesh BALASUBRAMANIAN
  • Patent number: 11637043
    Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: April 25, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
  • Publication number: 20230123089
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Daemian Raj Benjamin RAJ, Amit Kumar BANSAL, Juan Carlos ROCHA-ALVAREZ, Gregory Eugene CHICHKANOFF, Xinhai HAN, Masaki OGATA, Kristopher ENSLOW, Wenjiao WANG
  • Patent number: 11622489
    Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Thomas Kwon, Xinhai Han