Patents by Inventor Xinhai Han
Xinhai Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946140Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.Type: GrantFiled: March 26, 2021Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Anantha K. Subramani, Seyyed Abdolreza Fazeli, Yang Guo, Ramcharan Sundar, Arun Kumar Kotrappa, Steven Mosbrucker, Steven D. Marcus, Xinhai Han, Kesong Hu, Tianyang Li, Philip A. Kraus
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Patent number: 11948846Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.Type: GrantFiled: April 4, 2023Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Patent number: 11898249Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.Type: GrantFiled: February 13, 2023Date of Patent: February 13, 2024Assignee: Applied Materials, Inc.Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Wenyoung Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward W. Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik, Ganesh Balasubramanian
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Publication number: 20240044000Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Inventors: Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Daemian Raj BENJAMIN RAJ, Amit Kumar BANSAL, Juan Carlos ROCHA-ALVAREZ, Gregory Eugene CHICHKANOFF, Xinhai HAN, Masaki OGATA, Kristopher ENSLOW, Wenjiao WANG
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Publication number: 20240045399Abstract: A method includes receiving time trace sensor data associated with a substrate processing procedure. The substrate processing procedure includes two or more sets of processing conditions. At least a first set of processing conditions and a second set of processing conditions each include one or more operations performed repeatedly. The method further includes separating a first and second portion of the time trace sensor data corresponding to the first and second sets of processing conditions into a first and second plurality of cycle data. The method further includes processing the first plurality of cycle data and the second plurality of cycle data to generate summary data. The method further includes providing an alert to a user. The alert is based on the summary data.Type: ApplicationFiled: May 17, 2022Publication date: February 8, 2024Inventors: Qinglin Chai, Yue Ma, Liming Zhang, Xinhai Han, Chuan Ying Wang
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Patent number: 11851759Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.Type: GrantFiled: December 16, 2022Date of Patent: December 26, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Gregory Eugene Chichkanoff, Xinhai Han, Masaki Ogata, Kristopher Enslow, Wenjiao Wang
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Patent number: 11837448Abstract: Examples disclosed herein relate to a method and apparatus for cleaning and repairing a substrate support having a heater disposed therein. A method includes (a) cleaning a surface of a substrate support having a bulk layer, the substrate support is disposed in a processing environment configured to process substrates. The cleaning process includes forming a plasma at a high temperature from a cleaning gas mixture having a fluorine containing gas and oxygen. The method includes (b) removing oxygen radicals from the processing environment with a treatment plasma formed from a treatment gas mixture. The treatment gas mixture includes the fluorine containing gas. The method further includes (c) repairing an interface of the substrate support and the bulk layer with a post-treatment plasma. The post-treatment plasma is formed from a post-treatment gas mixture including a nitrogen containing gas. The high temperature is greater than or equal to about 500 degrees Celsius.Type: GrantFiled: April 27, 2021Date of Patent: December 5, 2023Assignee: Applied Materials, Inc.Inventors: Shuran Sheng, Lin Zhang, Jiyong Huang, Jang Seok Oh, Joseph C. Werner, Nitin Khurana, Ganesh Balasubramanian, Jennifer Y. Sun, Xinhai Han, Zhijun Jiang
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Publication number: 20230359179Abstract: An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Inventors: Mitesh Sanghvi, Venkatanarayana Shankarmurthy, Yulian Yao, Chuan Ying Wang, Xinhai Han
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Patent number: 11776835Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.Type: GrantFiled: September 29, 2020Date of Patent: October 3, 2023Assignee: Applied Materials, Inc.Inventors: Zheng John Ye, Daemian Raj Benjamin Raj, Rana Howlader, Abhigyan Keshri, Sanjay G. Kamath, Dmitry A. Dzilno, Juan Carlos Rocha-Alvarez, Shailendra Srivastava, Kristopher R. Enslow, Xinhai Han, Deenesh Padhi, Edward P. Hammond
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Publication number: 20230238289Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.Type: ApplicationFiled: April 4, 2023Publication date: July 27, 2023Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Publication number: 20230193466Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Michael Wenyoung TSIANG, Masaki OGATA, Zhijun JIANG, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Jianhua ZHOU, Ramprakash SANKARAKRISHNAN, Amit Kumar BANSAL, Jeongmin LEE, Todd EGAN, Edward W. BUDIARTO, Dmitriy PANASYUK, Terrance Y. LEE, Jian J. CHEN, Mohamad A. AYOUB, Heung Lak PARK, Patrick REILLY, Shahid SHAIKH, Bok Hoen KIM, Sergey STARIK, Ganesh BALASUBRAMANIAN
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Patent number: 11637043Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.Type: GrantFiled: November 3, 2020Date of Patent: April 25, 2023Assignee: Applied Materials, Inc.Inventors: Wenjiao Wang, Joshua Maher, Xinhai Han, Deenesh Padhi, Tza-Jing Gung
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Publication number: 20230123089Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Inventors: Shailendra SRIVASTAVA, Sai Susmita ADDEPALLI, Nikhil Sudhindrarao JORAPUR, Daemian Raj Benjamin RAJ, Amit Kumar BANSAL, Juan Carlos ROCHA-ALVAREZ, Gregory Eugene CHICHKANOFF, Xinhai HAN, Masaki OGATA, Kristopher ENSLOW, Wenjiao WANG
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Patent number: 11622489Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.Type: GrantFiled: September 16, 2021Date of Patent: April 4, 2023Assignee: Applied Materials, Inc.Inventors: Thomas Kwon, Xinhai Han
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Patent number: 11613812Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.Type: GrantFiled: September 3, 2020Date of Patent: March 28, 2023Assignee: Applied Materials, Inc.Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Wenyoung Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik, Ganesh Balasubramanian
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Publication number: 20230093330Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Thomas Kwon, Xinhai Han
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Patent number: 11569257Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.Type: GrantFiled: May 29, 2020Date of Patent: January 31, 2023Assignee: Applied Materials, Inc.Inventors: Xinhai Han, Deenesh Padhi, Er-Xuan Ping, Srinivas Guggilla
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Patent number: 11538677Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.Type: GrantFiled: September 1, 2020Date of Patent: December 27, 2022Assignee: Applied Materials, Inc.Inventors: Chuanxi Yang, Hang Yu, Yu Yang, Chuan Ying Wang, Allison Yau, Xinhai Han, Sanjay G. Kamath, Deenesh Padhi
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Patent number: 11530482Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.Type: GrantFiled: June 5, 2020Date of Patent: December 20, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Gregory Eugene Chichkanoff, Xinhai Han, Masaki Ogata, Kristopher Enslow, Wenjiao Wang
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Patent number: 11515324Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.Type: GrantFiled: December 19, 2019Date of Patent: November 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Thomas Kwon, Xinhai Han