Abstract: In one implementation, a method comprising depositing one or more silicon oxide/silicon nitride containing stacks on a substrate positioned in a processing chamber is provided. Depositing the one or more silicon oxide/silicon nitride containing stacks comprises (a) energizing a first process gas into a first plasma, (b) depositing a first film layer over the substrate from the first plasma, (c) energizing a second process gas into a second plasma, wherein the second process gas comprises a compound having at least one silicon-nitrogen bond and (d) depositing a second film layer on the first film layer from the second plasma. The method further comprises repeating (a), (b), (c), and (d) until a predetermined number of first film layers and second film layers have been deposited on the substrate. The first film layer is a silicon oxide layer and the second film layer is a silicon nitride layer.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

Abstract: Methods for depositing hardmask materials and films, and more specifically, for depositing phosphorus-doped, silicon nitride films are provided. A method of depositing a material on a substrate in a processing chamber includes exposing a substrate to a deposition gas in the presence of RF power to deposit a phosphorus-doped, silicon nitride film on the substrate during a plasma-enhanced chemical vapor deposition (PE-CVD) process. The deposition gas contains one or more silicon precursors, one or more nitrogen precursors, one or more phosphorus precursors, and one or more carrier gases. The phosphorus-doped, silicon nitride film has a phosphorus concentration in a range from about 0.1 atomic percent (at %) to about 10 at %.

Abstract: Embodiments of the disclosure describe an apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1?x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

Abstract: Implementations of the present disclosure generally provide improved methods for cleaning a vacuum chamber to remove adsorbed contaminants therefrom prior to a chamber seasoning process while maintaining the chamber at desired deposition processing temperatures. The contaminants may be formed from the reaction of cleaning gases with the chamber components and the walls of the vacuum chamber.

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may further include depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer or a stress layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method may include depositing a second silicon layer on the first silicon nitride layer. The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: A method is provided for forming a stack of film layers for use in 3D memory devices. The method starts with providing a substrate in a processing chamber of a deposition reactor. Then one or more process gases suitable for forming a dielectric layer are supplied into the processing chamber of the deposition reactor forming a dielectric layer on the substrate. Then one or more process gases suitable for forming a metallic layer are supplied into the processing chamber of the deposition reactor forming a metallic layer on the dielectric layer. Then one or more process gases suitable for forming a metallic nitride adhesion layer are supplied into the processing chamber of the deposition reactor forming a metallic nitride adhesion layer on the metallic layer. The sequence is then repeated to form a desired number of layers.

Abstract: Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: A method and apparatus for a dual-channel showerhead is provided. In one embodiment the showerhead comprises a body comprising a conductive material having a plurality of first openings formed therethrough comprising a first gas channel and a plurality of second openings formed therethrough comprising a second gas channel that is fluidly separated from the first gas channel, wherein each of the first openings having a geometry that is different than each of the second openings.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.