Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: Examples disclosed herein relate to a method and apparatus for cleaning and repairing a substrate support having a heater disposed therein. A method includes (a) cleaning a surface of a substrate support having a bulk layer, the substrate support is disposed in a processing environment configured to process substrates. The cleaning process includes forming a plasma at a high temperature from a cleaning gas mixture having a fluorine containing gas and oxygen. The method includes (b) removing oxygen radicals from the processing environment with a treatment plasma formed from a treatment gas mixture. The treatment gas mixture includes the fluorine containing gas. The method further includes (c) repairing an interface of the substrate support and the bulk layer with a post-treatment plasma. The post-treatment plasma is formed from a post-treatment gas mixture including a nitrogen containing gas. The high temperature is greater than or equal to about 500 degrees Celsius.

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.

Abstract: An apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes are provided. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.

Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

Abstract: Exemplary semiconductor processing chambers may include a showerhead. The chambers may also include a substrate support characterized by a first surface facing the showerhead. The first surface may be configured to support a semiconductor substrate. The substrate support may define a recessed pocket centrally located within the first surface. The recessed pocket may be defined by an outer radial wall characterized by a height from the first surface within the recessed pocket that is greater than or about 150% of a thickness of the semiconductor substrate.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.