Patents by Inventor Xinhai Han

Xinhai Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9458537
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 4, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Wenyoung Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik, Ganesh Balasubramanian
  • Publication number: 20160203971
    Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.
    Type: Application
    Filed: October 8, 2015
    Publication date: July 14, 2016
    Inventors: Michael TSIANG, Praket P. JHA, Xinhai HAN, Nagarajan RAJAGOPALAN, Bok Hoen KIM, Tsutomu KIYOHARA, Subbalakshmi SREEKALA
  • Publication number: 20160017497
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Application
    Filed: September 29, 2015
    Publication date: January 21, 2016
    Inventors: NAGARAJAN RAJAGOPALAN, Xinhai HAN, Michael TSIANG, Masaki OGATA, Zhijun JIANG, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Jianhua ZHOU, Ramprakash SANKARAKRISHNAN, Amit Kumar BANSAL, Jeongmin LEE, Todd EGAN, Edward BUDIARTO, Dmitriy PANASYUK, Terrance Y. LEE, Jian J. CHEN, Mohamad A. AYOUB, Heung Lak PARK, Patrick REILLY, Shahid SHAIKH, Bok Hoen KIM, Sergey STARIK, Ganesh BALASUBRAMANIAN
  • Patent number: 9157730
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 13, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Ganesh Balasubramanian, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik
  • Publication number: 20150226540
    Abstract: Apparatus and method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Application
    Filed: October 23, 2013
    Publication date: August 13, 2015
    Applicant: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Michael Tsiang, Masaki Ogata, Zhijun Jiang, Juan Carlos Rocha-Alvarez, Thomas Nowak, Jianhua Zhou, Ramprakash Sankarakrishnan, Ganesh Balasubramanian, Amit Kumar Bansal, Jeongmin Lee, Todd Egan, Edward Budiarto, Dmitriy Panasyuk, Terrance Y. Lee, Jian J. Chen, Mohamad A. Ayoub, Heung Lak Park, Patrick Reilly, Shahid Shaikh, Bok Hoen Kim, Sergey Starik
  • Publication number: 20150206757
    Abstract: A method is provided for forming a stack of film layers for use in 3D memory devices. The method starts with providing a substrate in a processing chamber of a deposition reactor. Then one or more process gases suitable for forming a dielectric layer are supplied into the processing chamber of the deposition reactor forming a dielectric layer on the substrate. Then one or more process gases suitable for forming a metallic layer are supplied into the processing chamber of the deposition reactor forming a metallic layer on the dielectric layer. Then one or more process gases suitable for forming a metallic nitride adhesion layer are supplied into the processing chamber of the deposition reactor forming a metallic nitride adhesion layer on the metallic layer. The sequence is then repeated to form a desired number of layers.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 23, 2015
    Inventors: XINHAI HAN, Nagarajan Rajagopalan, Sung Hyun Hong, Bok Hoen Kim, Mukund Srinivasan
  • Publication number: 20140287593
    Abstract: Methods and apparatus for high rate formation of multi-layer stacks on semiconductor substrate is provided. A chamber for forming such stacks at high rates includes a first precursor line and a second precursor line. The first precursor line is coupled to a first diverter, which is coupled to a gas inlet in a lid assembly of the chamber. The second precursor line is coupled to a second diverter, which is also coupled to the gas inlet. The first diverter is also coupled to a first divert line, and the second diverter is coupled to a second divert line. Each of the first and second divert lines is coupled to a divert exhaust system. A chamber exhaust system is coupled to the chamber. The diverters are typically located close to the lid assembly.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 25, 2014
    Inventors: Xinhai HAN, Zhijun JIANG, Nagarajan RAJAGOPALAN, Bok Hoen KIM, Ramprakash SANKARAKRISHNAN, Ganesh BALASUBRAMANIAN, Juan Carlos ROCHA- ALVAREZ, Mukund SRINIVASAN
  • Publication number: 20140272184
    Abstract: Methods for maintaining clean etch rate and reducing particulate contamination with PECVD of amorphous silicon films are provided. The method comprises cleaning a processing chamber with a plasma comprising a cleaning gas, exposing at least a portion of the interior surfaces and components of the processing chamber to an oxidation gas and a nitration gas in the presence of a plasma and depositing a bi-layer seasoning layer on the interior surfaces and components of the processing chamber.
    Type: Application
    Filed: February 12, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Subbalakshmi SREEKALA, Xinhai HAN, Nagarajan RAJAGOPALAN, Bok Hoen KIM, Yoichi SUZUKI, Tsutomu KIYOHARA
  • Publication number: 20140118751
    Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.
    Type: Application
    Filed: October 17, 2013
    Publication date: May 1, 2014
    Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Michael TSIANG, Masaki OGATA, Zhijun JIANG, Juan Carlos ROCHA-ALVAREZ, Thomas NOWAK, Jianhua ZHOU, Ramprakash SANKARAKRISHNAN, Amit Kumar BANSAL, Jeongmin LEE, Todd EGAN, Edward BUDIARTO, Dmitriy PANASYUK, Terrance Y. LEE, Jian J. CHEN, Mohamad A. AYOUB, Heung Lak PARK, Patrick REILLY, Shahid SHAIKH, Bok Hoen KIM, Sergey STARIK, Ganesh BALASUBRAMANIAN
  • Patent number: 8563095
    Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: October 22, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Ryan Yamase, Ji Ae Park, Shamik Patel, Thomas Nowak, Zhengjiang “David” Cui, Mehul Naik, Heung Lak Park, Ran Ding, Bok Hoen Kim
  • Publication number: 20130161629
    Abstract: Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550° C.; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600° C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700° C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: XINHAI HAN, NAGARAJAN RAJAGOPALAN, GUANGCHI XUAN, JIANHUA ZHOU, JIGANG LI, SHAHID SHAIKH, PATRICK REILLY, THOMAS NOWAK, JUAN CARLOS ROCHA-ALVAREZ, HEUNG LAK PARK, BOK HOEN KIM
  • Patent number: 8298887
    Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim
  • Patent number: 8076250
    Abstract: A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: December 13, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Ji Ae Park, Tsutomu Kiyohara, Sohyun Park, Bok Hoen Kim
  • Publication number: 20110223765
    Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Ryan YAMASE, Ji Ae PARK, Shamik PATEL, Thomas NOWAK, Zhengjiang "David" CUI, Mehul NAIK, Heung Lak PARK, Ran DING, Bok Hoen KIM
  • Publication number: 20110136327
    Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.
    Type: Application
    Filed: June 25, 2010
    Publication date: June 9, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim