Patents by Inventor Xinhui Wang

Xinhui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9694061
    Abstract: Disclosed herein are isolated human monoclonal antibodies, and functional fragments thereof, that specifically bind HMW-MAA. Nucleic acids encoding these antibodies, expression vectors including these nucleic acid molecules, and isolated host cells that express the nucleic acid molecules are also disclosed. The antibodies can be used to detect HMW-MAA in a sample. Methods of diagnosing cancer, or confirming a diagnosis of cancer, are disclosed herein that utilize these antibodies. Methods of treating a subject with cancer are also disclosed.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 4, 2017
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Xinhui Wang, Soldano Ferrone
  • Patent number: 9679917
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricardo A. Donaton, Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage
  • Publication number: 20170117281
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 9576964
    Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESSS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Babar A. Khan, Dae-Gyu Park, Xinhui Wang
  • Patent number: 9576096
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 9564444
    Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.
    Type: Grant
    Filed: October 3, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Babar A. Khan, Dae-Gyu Park, Xinhui Wang
  • Publication number: 20170025418
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Application
    Filed: October 5, 2016
    Publication date: January 26, 2017
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Publication number: 20170005098
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
  • Patent number: 9406683
    Abstract: A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Russell H. Arndt, Babar A. Khan, Byeong Y. Kim, Xinhui Wang
  • Publication number: 20160207990
    Abstract: Isolated monoclonal antibodies are disclosed herein that specifically bind endoplasmin. In some embodiments these antibodies are fully human. Recombinant nucleic acids encoding these antibodies, expression vectors including these nucleic acids, and host cells transformed with these expression vectors are also disclosed herein. In several embodiments the disclosed antibodies are of use for detecting and/or treating tumors that express endoplasmin, such as melanoma, breast cancer, head and neck squamous cell carcinoma, renal cancer, lung cancer, glioma, bladder cancer, ovarian cancer or pancreatic cancer. In one example, the tumor is a melanoma.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 21, 2016
    Applicant: University of Pittsburgh - Of The Commonwealth Sys tem of Higher Education
    Inventors: Soldano Ferrone, Xinhui Wang, Thomas P. Conrads, Elvira Favoino, Brian L. Hood
  • Patent number: 9385131
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix Beaudoin, Stephen M. Lucarini, Xinhui Wang, Xinlin Wang
  • Publication number: 20160181249
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming a plurality of fin structures from a substrate material. The method further includes forming a deep trench capacitor structure, contacting at least selected fin structures. The method further includes forming a liner over the deep trench capacitor structure. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structure protecting the deep trench capacitor structure during deposition and etching processes.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Guillaume D. BRIEND, Ricardo A. DONATON, Herbert L. HO, Donghun KANG, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
  • Publication number: 20160181253
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Ricardo A. DONATON, Babar A. KHAN, Xinhui WANG, Deepal WEHELLA-GAMAGE
  • Publication number: 20160163711
    Abstract: A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 9, 2016
    Inventors: Russell H. Arndt, Babar A. Khan, Byeong Y. Kim, Xinhui Wang
  • Patent number: 9340608
    Abstract: Isolated monoclonal antibodies are disclosed herein that specifically bind endoplasmin. In some embodiments these antibodies are fully human. Recombinant nucleic acids encoding these antibodies, expression vectors including these nucleic acids, and host cells transformed with these expression vectors are also disclosed herein. In several embodiments the disclosed antibodies are of use for detecting and/or treating tumors that express endoplasmin, such as melanoma, breast cancer, head and neck squamous cell carcinoma, renal cancer, lung cancer, glioma, bladder cancer, ovarian cancer or pancreatic cancer. In one example, the tumor is a melanoma.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 17, 2016
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Soldano Ferrone, Xinhui Wang, Thomas P. Conrads, Elvira Favoino, Brian L. Hood
  • Publication number: 20160099249
    Abstract: At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.
    Type: Application
    Filed: October 3, 2015
    Publication date: April 7, 2016
    Inventors: Kevin K. Chan, Babar A. Khan, Dae-Gyu Park, Xinhui Wang
  • Patent number: 9296811
    Abstract: Combinations of agents that have a synergistic effect for the treatment of a tumor are disclosed herein. These combinations of agents can be used to treat tumors, wherein the cells of the cancer express a mutated BRAF. Methods are disclosed for treating a subject diagnosed with a tumor that expresses a mutated BRAF. The methods include administering to the subject (1) a therapeutically effective amount of an antibody or antigen binding fragment thereof that specifically binds high molecular weight melanoma associated antigen (HMW-MAA), also known as CSPG4; and (2) a therapeutically effective amount of a BRAF inhibitor. In some embodiments, the tumor is melanoma. In some embodiments the method includes selecting a subject with primary or secondary resistance to a BRAF inhibitor. In further embodiments, treating the tumor comprises decreasing the metastasis of the tumor. In additional embodiments, the BRAF inhibitor comprises PLX4032 or PLX4720.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 29, 2016
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Soldano Ferrone, Xinhui Wang, Elvira Favoino, Ling Yu, Yangyang Wang
  • Patent number: 9287136
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Patent number: 9275907
    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kevin K. Chan, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Min Yang, Qi Zhang
  • Publication number: 20160045598
    Abstract: Methods for treating cancer using a combination of an inhibitor of the sonic hedgehog signaling pathway (e.g., LDE225) with radiation and a tumor antigen-specific monoclonal antibody (e.g., heat shock protein (HSP) glucose regulated protein of 94000 daltons (Grp94)-specific mAb W9, or chondroitin sulfate proteoglycan 4 (CSPG4)-targeted mAbs), or with a BRAF inhibitor, e.g., in BRAF inhibitor resistant cancers.
    Type: Application
    Filed: April 3, 2014
    Publication date: February 18, 2016
    Inventors: Francesco Sabbatino, Yangyang Wang, Xinhui Wang, Steven Isakoff, Cristina Ferrone, Joe Schwab, Soldano Ferrone