Patents by Inventor Ya Chen

Ya Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10630319
    Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ju-Ya Chen, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee
  • Publication number: 20200107354
    Abstract: Various examples and schemes pertaining to New Radio (NR) vehicle-to-everything (V2X) cluster management are described. An apparatus, implemented in a user equipment (UE) of a V2X cluster in an NR V2X communication environment, receives a scheduling request from a member of the V2X cluster. The apparatus transmits a resource grant to the member to allocate a resource of one or more resources to the member responsive to the receiving of the scheduling request. The one or more resources are either: (a) preconfigured by a wireless network, or (b) granted by the wireless network responsive to the UE transmitting a resource request to the wireless network upon receiving the scheduling request.
    Type: Application
    Filed: November 1, 2019
    Publication date: April 2, 2020
    Inventors: Ju-Ya Chen, Chien-Yi Wang, Ahmet Umut Ugurlu
  • Publication number: 20200107395
    Abstract: Various examples and schemes pertaining to methods and apparatus of a New Radio (NR) vehicle-to-everything (V2X) cluster head are described. An apparatus implemented as a source user equipment (UE) determines whether there is a need to either join a cluster or become a cluster head in an NR V2X communication environment. The apparatus also detects whether there is any existing cluster head in the NR V2X communication environment responsive to determining that there is the need. The apparatus then determines whether to join a first cluster associated with a first cluster head responsive to the first cluster head being detected as an existing cluster head in the NR V2X communication environment.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Inventors: Ju-Ya Chen, Chien-Yi Wang, Ahmet Umut Ugurlu
  • Publication number: 20200107171
    Abstract: Various examples and schemes pertaining to on-demand network configuration of vehicle-to-everything (V2X) user equipment (UE) autonomy in New Radio (NR) mobile communications are described. An apparatus implemented in a first user equipment (UE) receives a signaling from a network node of a wireless network. Based on the signaling, the apparatus operates simultaneously in a network-controlled mode and an autonomous mode such that: (a) the first UE operates in the network-controlled mode with respect to resource allocation on a first sidelink with a second UE, and (b) the first UE operates in the autonomous mode with respect to resource allocation on a second sidelink with the second UE or a third UE.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Inventors: Ju-Ya Chen, Ahmet Umut Ugurlu
  • Publication number: 20200107170
    Abstract: Various examples and schemes pertaining to sidelink resource allocation for vehicle-to-everything (V2X) in New Radio (NR) mobile communications are described. An apparatus implemented in a first user equipment (UE) receives a first signaling from a network node of a wireless network, with the first signaling configuring a first sidelink resource for a sidelink between the first UE and a second UE. The apparatus transmits a packet or transport block (TB) to the second UE on the sidelink using the configured first sidelink resource. The apparatus also receives a second signaling from the network node responsive to the second UE failing to decode the packet or TB, with the second signaling dynamically configuring a second sidelink resource for the sidelink. The apparatus then retransmits the packet or TB to the second UE on the sidelink using the dynamically configured second sidelink resource.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Inventors: Ju-Ya Chen, Ahmet Umut Ugurlu
  • Patent number: 10608665
    Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 31, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chong-You Lee, Timothy Perrin Fisher-Jeffes, Maoching Chiu, Wei Jen Chen, Cheng-Yi Hsu, Ju-Ya Chen, Yen Shuo Chang
  • Publication number: 20200093395
    Abstract: The present disclosure provides apparatuses and computer readable media for measuring sub-epidermal moisture in patients to determine damaged tissue for clinical intervention. The present disclosure also provides methods for determining damaged tissue.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: Bruin Biometrics, LLC
    Inventors: Ya-Chen TONAR, Shannon RHODES, Marta CLENDENIN, Martin BURNS, Kindah JARADEH
  • Patent number: 10601544
    Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: March 24, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chong-You Lee, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
  • Publication number: 20200083126
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
  • Patent number: 10581457
    Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 3, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Timothy Perrin Fisher-Jeffes, Chong-You Lee, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Patent number: 10567116
    Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 18, 2020
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Chong-You Lee, Timothy Perrin Fisher-Jeffes, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20200053528
    Abstract: Sidelink vehicle-to-everything (V2X) transmission is performed over a Physical Sidelink Control Channel (PSCCH) and a Physical Sidelink Shared Channel (PSSCH). Encoded control information is transmitted in the PSCCH and encoded data is transmitted in the PSSCH. The PSCCH uses a first portion of the time-and-frequency resources, and the PSSCH uses and a second portion of the time-and-frequency resources. A first part of the PSSCH uses a first set of time resources overlapping with the PSCCH and a first set of frequency resources non-overlapping with the PSCCH. A second part of the PSSCH uses a second set of time resources non-overlapping with the PSCCH and a second set of frequency resources overlapping with the PSCCH.
    Type: Application
    Filed: July 24, 2019
    Publication date: February 13, 2020
    Inventors: Chien-Yi Wang, Ju-Ya Chen
  • Publication number: 20200022877
    Abstract: An infant bottle is provided. The infant bottle comprises an open-top receptacle for receiving liquid, a nipple sealably connectable to the open-top end of the receptacle, a formula compartment disposed adjacent the open-top end of the receptacle, an open-top end of the formula compartment corresponding and fitted within the open-top end of the receptacle, and a formula release mechanism to empty the contents contained in the formula compartment into the receptacle. A removable warming cover substantially covering at least a portion of the outer surface of the receptacle and comprising a sleeve of material for receiving the receptacle, a base comprising a rechargeable battery, and a heating element operatively connected to the battery, is also provided. A method of using the same is also provided.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 23, 2020
    Inventors: LIANG LI, Ya Chen
  • Patent number: 10542504
    Abstract: A wireless communication system and method is provided. The wireless communication system includes a wireless transceiver device and a processing device. The processing device includes a direction control module, a power adjusting module and a boundary setting module. The direction control module controls the scanning direction and generates a point direction information record according to each reference position respectively. The power adjusting module adjusts the transmitting power and generates a point power information record according to each reference position and the corresponding point direction information record respectively. The boundary setting module generates a boundary information record. The processing device controls the transmitting direction and the transmitting power according to the point direction information record(s), the point power information record(s) and the boundary information record, so as to limit a transmission of the wireless signal within a specific area.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 21, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yin-Chang Liu, Hsuan-Lin Cheng, Chih-Wei Wang, Chun-Yi Lu, Ya-Chen Chuang, Chia-Yu Chen, Tsung-Han Tsai
  • Publication number: 20200020601
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
  • Patent number: 10535675
    Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
  • Patent number: 10535574
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
  • Patent number: 10522591
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Publication number: 20190394710
    Abstract: Various solutions for multiple active bandwidth parts (BWPs) operation with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a configuration of a plurality of BWPs. The apparatus may determine whether a restriction is configured. The apparatus may activate the plurality of BWPs on a same carrier according to the restriction. The apparatus may perform a transmission or reception on at least one of a plurality of activated BWPs.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Inventors: Ahmet Umut Ugurlu, Ju-Ya Chen
  • Publication number: 20190372600
    Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Inventors: Wei-Jen Chen, Ju-Ya Chen, Yen-Shuo Chang, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Cheng-Yi Hsu, Chong-You Lee