Abstract: A delivery device for delivering medicament, such as insulin, to a patient includes a housing and a base enclosing an inner cavity. Enclosed within the housing is a reservoir for containing a medicament, a delivery mechanism for delivering the medicament to the patient, and a pump in fluid communication with the reservoir and delivery mechanism. The base has an integrally formed fluid channel covered by a flexible membrane in fluid communication with the reservoir and the delivery mechanism. A peristaltic pump mechanism includes a cam assembly having a plurality of cams and cam follower assembly with a plurality of protrusions to sequentially engaging the flexible membrane to advance the fluid through fluid channel.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Abstract: A method for determining flow velocity distribution in the roughness sublayer is provided, which uses the experimental device that includes a variable-slope circulating flume system and a flow-measuring system, the variable-slope circulating flume system is used to study flow in the roughness sublayer, and the flow-measuring system is used to measure flow velocity in each zone in the flume. In the variable-slope circulating flume, the method according to the invention uses cylindrical aluminum rods to simulate large-scale roughness elements, and the submergence, the average bulk flow velocity and the distribution density of roughness elements are changed.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: Methods, systems, and apparatus are presented for providing enhanced scheduling requests, e.g., in an IEEE 802.11 network. A client station (STA) may determine one or more minimum quality of service (QoS) metrics for supporting an application being implemented by the STA, and may determine minimum scheduling parameters to be implemented by an access point (AP) to achieve the minimum QoS. The STA may transmit to the AP a specific scheduling request indicating the minimum scheduling parameters. In response, the AP may schedule communication resources for the STA in accordance with the minimum scheduling resources.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate comprises a base substrate, and a first thin film transistor and a second thin film transistor formed on the base substrate, wherein a first active layer of the first thin film transistor is made of low-temperature polysilicon, and a second active layer of the second thin film transistor is made of a metal oxide. The display substrate further comprises a first barrier layer on a side of the second active layer close to the base substrate and a second barrier layer on a side of the second active layer away from the base substrate. The orthographic projection of the second active layer onto the base substrate falls within the orthographic projections of the first barrier layer and the second barrier layer onto the base substrate.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: Some embodiments of this disclosure include apparatuses and methods for implementing a target wake time (TWT) scheme that includes traffic differentiation and service period extension. For example some embodiments relate to an electronic device including a transceiver and one or more processors communicatively coupled to the transceiver. The one or more processors receive an indication of traffic associated with an application. The one or more processors determine information associated with the traffic and configure the TWT scheme associated with the traffic based at least in part on the determined information. The one or more processors further communicate initial information associated with the TWT scheme to an access point of a wireless network. The initial information associated with the TWT scheme can include at least one of traffic direction information, traffic pattern information, a traffic identifier (TID), or an access category, indication (ACID).

Abstract: A throttling device, including a tank for accommodating liquid refrigerant, with an orifice plate arranged at an outlet of the tank; a floating ball capable of floating on a liquid surface of the refrigerant; a pivot rod pivotally fixed on the tank through a pivot shaft; a connecting rod, with one end thereof fixedly connected with the floating ball, and the other end thereof fixedly connected with the pivot rod; a valve plate fixed on the pivot rod and located near an orifice of the orifice plate, wherein the valve plate is capable of adjusting a flow area of the orifice under the action of the pivot rod; and a limit piece located above the valve plate and being movable to limit the valve plate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.

Abstract: The present application relates to a touch display screen and a mobile terminal. The touch display screen comprises a flat display area, a curved display area and a circuit area which are connected in sequence; the curved display area is bent to be arc-shaped; and the circuit area is located below the flat display area, wherein the touch display screen further comprises a plurality of touch lines, and signal input ends of the plurality of touch lines are all located in the circuit area.

Abstract: Predictive rendering (also referred to herein as speculative rendering) is disclosed. The predictive rendering is performed by an endpoint browser in response to a user input made by a user. The predictive rendering is verified using a surrogate browser that is executed on a remote server. The verification can be performed asynchronously.

Abstract: A display substrate includes a flexible substrate, a cathode layer located on a first side of the flexible substrate and at least one insulating layer located between the flexible substrate and the cathode layer. The flexible substrate includes at least one stretchable region, the stretchable region extends from the display area to the non-display area, and the stretchable region is provided with a plurality of holes arranged in an array therein. A border of the cathode layer is located in the non-display area. The at least one insulating layer is configured to expose the plurality of holes, the at least one insulating layer is provided with at least one partition groove therein, an orthographic projection of a partition groove on the flexible substrate is disposed around a hole of the plurality of holes, and the partition groove is configured to partition the cathode layer.

Abstract: A method of generating text in a first language for incorporation into a remote desktop image to be displayed at a client device, based on inputs made at the client device in a second language different from the first language includes the steps of: transmitting the inputs at the client device in the second language to a remote device that is generating the remote desktop image; generating candidate text in the first language at the client device based on the inputs made at the client device in the second language; upon selection of the candidate text at the client device, transmitting the candidate text to the remote device for incorporation of the candidate text into an updated remote desktop image; and upon receipt of the updated remote desktop image, displaying the updated remote desktop image at the client device.

Abstract: Disclosed are a display substrate, a manufacturing method thereof, a display panel and a display device. The display panel comprises: a base substrate provided with a first area and a second area which are not overlapped with each other; a low temperature poly-silicon transistor arranged in the first area, the low temperature poly-silicon transistor comprises a poly-silicon active layer; an oxide transistor arranged in the second area, the oxide transistor comprises a first gate electrode; the first gate electrode is arranged in a same layer as the poly-silicon active layer, and a material of the first gate electrode is heavily-doped poly-silicon.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: In an access control method, a service access request of a service application is received. The service access request includes identity information of a user. An identity validation request is sent to a server. The identity validation request includes the identity information of the user. Challenge information is received from the server based on the identity information of the user in the identity validation request being determined to be valid. Signature information of the challenge information is generated based on the challenge information and a private key. The signature information is sent to the server. A signature valid message is received from the server based on the challenge information being obtained from the signature information with a public key associated with the identity information of the user. Based on the signature valid message, the service access request is sent to the server.