Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.

Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.

Abstract: Disclosed herein are compounds, compositions and methods for treating tumors, particularly tumors that metastasize, via inhibiting tumor cells-induced platelet aggregation. The compound of the present disclosure has the formula (I), wherein, n is 2 or 3.

Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.

Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programing of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programing of the third memory cell. The first bias and the third bias are different.

Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias and the third bias are different.

Abstract: “A method for operating a memory array includes an all programming step, an erasing step and a selectively programming step. The all programming step is to program all of memory cells of a NAND string. The erasing step is to erase the all of the memory cells of the string after the all programming step. The selectively programming step is to program a portion of the all of memory cells of the NAND string after the erasing step. The NAND string includes a pillar channel layer, a pillar memory layer and control gates. The pillar memory layer is surrounded by the control gates separated from each other. The memory cells are defined at intersections of the pillar channel layer and the control gates.

Abstract: A method for detecting loss of network packets based on SDN includes selecting a data stream on a network path where the network path includes a plurality of switches. Start marking packet and end marking packet are created by a controller and the start marking packet is inserted in the data stream flowing through the first switch. After a time interval, the end marking packet is inserted. The respective arrivals of the start and end marking packets are reported to the controller by each switch on the network path. An absolute packet value between the start marking packet and the end marking packet flowing through each switch is calculated and a ratio of loss of network packets is calculated. The network path is adjusted and optimized according to the network packet loss ratios.

Abstract: Disclosed are 5-nitrobenzoate derivatives of Formula I, and the preparation method therefor, wherein R is referred to hydrogen (H), unsubstituted, mono-substituted, di-substituted or tri-substituted benzoyl moiety. 5-Nitrobenzoare derivatives of Formula I do not affect the platelet aggregation, possesses the inhibitory activity related to the tumor cell-induced platelet aggregation (TCIPA), and further specifically inhibits podoplanin-induced platelet aggregation. Therefore, 5-nitrobenzoates of the invention are applicable in its therapeutic use as the novel therapeutic agent in preventing tumor metastasis.

Abstract: A memory cell with a composite top electrode is provided. A bottom electrode is disposed over a substrate. A switching dielectric having a variable resistance is disposed over the bottom electrode. A capping layer is disposed over the switching dielectric. A composite top electrode is disposed over and abutting the capping layer. The composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer. By having the disclosed composite top electrode, an interfacial oxidized layer is eliminated or less formed when exposing the composite top electrode for top electrode via formation, thereby improving RC properties between the top electrode and the top electrode via. A method for manufacturing the memory cell is also provided.

Abstract: The present disclosure is directed to systems and methods for a minimum-implant-area (MIA) aware detailed placement. In embodiments, the present disclosure clusters a violation cell with the cells having a same threshold voltage (Vt) and determines an optimal region for a cluster to minimize the wire-length. In further embodiments, an MIA-aware cell flipping technique minimizes a design area while satisfying the MIA constraint.

Abstract: A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

Abstract: A method for redistribution layer routing is proposed. The method at least comprises inputting information regarding a redistribution layer layout, at least one netlist, and a constraint file. Next, it is creating a concentric-circle model based on the information, the netlist and the constraint file. Subsequently, it is assigning at least one pre-assignment net to at least one redistribution layer according to the concentric-circle model. Finally, the redistribution layer routing is performed.

Abstract: A memory device includes N word lines, wherein the word lines include an ith word line coupled to an ith memory cell and an (i+1)th word line coupled to an (i+1)th memory cell which is disposed adjacent to the ith memory cell and is a programmed memory cell, and i is an integer from 0 to (N?2). A method of operating such a memory device method includes a reading step. In the reading step, a read voltage is provided to the ith word line, a first pass voltage is provided to the (i+1)th word line, and a second pass voltage is provided to the others of the word lines, wherein the second pass voltage is lower than the first pass voltage.

Abstract: The present disclosure is directed to systems and methods for a minimum-implant-area (MIA) aware detailed placement. In embodiments, the present disclosure clusters a violation cell with the cells having a same threshold voltage (Vt) and determines an optimal region for a cluster to minimize the wire-length. In further embodiments, an MIA-aware cell flipping technique minimizes a design area while satisfying the MIA constraint.