Abstract: A method for analog circuit placement is proposed. The method comprises inputting a plurality of modules, a netlist and a constraint file. Next, it is performing a step of establishing a QB-tree construction. Then, a node perturbation of QB-tree is performed after establishing the QB-tree construction. Subsequently, it is performing a step of a look-ahead constraint checking to check whether meet constraints of the constraint file or not, followed by performing a QB-tree packing when meet constraints of the constraint file. Next, it is performing a process of performing a cost evaluation.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.

Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion harrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method for manufacturing an integrated circuit (IC) is provided. An etch is performed into an upper surface of an insulating layer to form an opening. A plurality of electrode layers is formed filling the opening. Forming the plurality of electrode layers comprises repeatedly forming an electrode layer conformally lining an unfilled region of the opening until the opening is filled. Forming the electrode layer comprises depositing the electrode layer and treating a surface of the electrode layer that faces an interior of the opening. A planarization is performed into the plurality of electrode layers to the upper surface of the insulating layer.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a multi-layer capacitor dielectric layer including an amorphous dielectric layer configured to mitigate the formation of leakage paths, and a method of formation. In some embodiments, the MIM (metal-insulator-metal) capacitor has a capacitor bottom metal layer. A multi-layer capacitor dielectric layer is disposed over the capacitor bottom metal layer. The multi-layer capacitor dielectric layer has an amorphous dielectric layer abutting a high-k dielectric layer. A capacitor top metal layer is disposed over the multi-layer capacitor dielectric layer. The high-k dielectric layer within the capacitor dielectric layer provides the MIM capacitor with a high capacitance density, while the amorphous dielectric layer prevents leakage by blocking the propagation of grain boundaries between the capacitor top metal layer and the capacitor bottom metal layer.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method for analog circuit placement is proposed. The method comprises inputting a plurality of modules, a netlist and a constraint file. Next, it is performing a step of establishing a QB-tree construction. Then, a node perturbation of QB-tree is performed after establishing the QB-tree construction. Subsequently, it is performing a step of a look-ahead constraint checking to check whether meet constraints of the constraint file or not, followed by performing a QB-tree packing when meet constraints of the constraint file. Next, it is performing a process of performing a cost evaluation.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: Disclosed herein are compounds, compositions and methods for treating tumors, particularly tumors that metastasize, via inhibiting tumor cells-induced platelet aggregation. The compound of the present disclosure has the formula (I), wherein, n is 2 or 3.

Abstract: Disclosed are 5-nitrobenzoate derivatives of Formula I, and the preparation method therefor, wherein R is referred to hydrogen (H), unsubstituted, mono-substituted, di-substituted or tri-substituted benzoyl moiety. 5-Nitrobenzoare derivatives of Formula I do not affect the platelet aggregation, possesses the inhibitory activity related to the tumor cell-induced platelet aggregation (TCIPA), and further specifically inhibits podoplanin-induced platelet aggregation. Therefore, 5-nitrobenzoates of the invention are applicable in its therapeutic use as the novel therapeutic agent in preventing tumor metastasis.

Abstract: An embodiment of a memory device is disclosed. The memory device includes a multi-stack dielectric layer over a substrate; a first conductive layer over the multi-stack dielectric layer; a second conductive layer over the first conductive layer; a getter layer over the second conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride; and an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the first conductive layer.

Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Abstract: Disclosed are 5-nitrobenzoate derivatives of Formula I, and the preparation method therefor, wherein R is referred to hydrogen (H), unsubstituted, mono-substituted, di-substituted or tri-substituted benzoyl moiety. 5-Nitrobenzoare derivatives of Formula I do not affect the platelet aggregation, possesses the inhibitory activity related to the tumor cell-induced platelet aggregation (TCIPA), and further specifically inhibits podoplanin-induced platelet aggregation. Therefore, 5-nitrobenzoates of the invention are applicable in its therapeutic use as the novel therapeutic agent in preventing tumor metastasis.