Patents by Inventor Yao-Wen Chang

Yao-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR PERFORMING PROGRAM INHIBIT OPERATION WITH CELL DISTURBANCE ALLEVIATION, MEMORY DEVICE AND CONTROLLER
    Publication number: 20190378582
    Abstract: A method for performing a program inhibit operation with cell disturbance alleviation, a memory device and a controller are provided. The method includes the following steps. A verify operation is performed on a cell string of a cell array. A power pulse is applied on the cell string. The program inhibit operation is performed on the cell string. The step of applying the power pulse is performed before the step of performing the program inhibit operation.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: Tao-Yuan LIN, I-Chen YANG, Yao-Wen CHANG
  • FILM SCHEME FOR BUMPING
    Publication number: 20190378806
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 12, 2019
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Top electrode cap structure for embedded memory
    Patent number: 10505103
    Abstract: The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Tsung-Hsueh Yang
  • Method of Redistribution Layer Routing for 2.5-Dimensional Integrated Circuit Packages
    Publication number: 20190370433
    Abstract: A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Chun-Han CHIANG, Fu-Yu CHUANG, Yao-Wen CHANG, Chih-Che LIN, Chun-Yi YANG
  • Method to improve MIM device performance
    Patent number: 10497773
    Abstract: The present disclosure relates to a method of forming a MIM (metal-insulator-metal) capacitor using a post capacitor bottom metal (CBM) treatment process to reduce a roughness of a top surface of a capacitor bottom metal layer, and an associated apparatus. In some embodiments, the method is performed by forming a capacitor bottom metal layer having a first metal material over a semiconductor substrate. A top surface of the capacitor bottom metal layer is exposed to one or more post CBM treatment agents having oxygen. The one or more post CBM treatment agents reduce a roughness of the top surface and form an interface layer having the first metal material and oxygen onto and in direct contact with the top surface of the capacitor bottom metal layer. A capacitor dielectric layer is formed over the interface layer and a capacitor top metal layer is formed over the capacitor dielectric layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Semiconductor structure, electrode structure and method of forming the same
    Patent number: 10468587
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
  • METHOD FOR LEGALIZING MIXED-CELL HEIGHT STANDARD CELLS OF IC
    Publication number: 20190251224
    Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Chao-Hung WANG, Yen-Yi WU, Shih-Chun CHEN, Yao-Wen CHANG, Meng-Kai HSU
  • TOP ELECTRODE CAP STRUCTURE FOR EMBEDDED MEMORY
    Publication number: 20190245138
    Abstract: The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Yao-Wen Chang, Tsung-Hsueh Yang
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20190165110
    Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.
    Type: Application
    Filed: April 25, 2018
    Publication date: May 30, 2019
    Inventors: YAO-WEN CHANG, GUNG-PEI CHANG, CHING-SHENG CHU, CHERN-YOW HSU
  • STRUCTURE AND METHOD TO EXPOSE MEMORY CELLS WITH DIFFERENT SIZES
    Publication number: 20190157099
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 23, 2019
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • MIM capacitor, semiconductor structure including MIM capacitors and method for manufacturing the same
    Patent number: 10290701
    Abstract: A MIM capacitor includes a bottom electrode, a middle electrode disposed over the bottom electrode, a top electrode disposed over the middle electrode, a first dielectric layer sandwiched between the bottom electrode and the middle electrode, and a second dielectric layer sandwiched between the middle electrode and the top electrode. A surface of the bottom electrode and a surface of the top electrode respectively comprise a Ra value lower than 0.35 nm and a Rq value lower than 0.4 nm.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yao-Wen Chang
  • Top electrode cap structure for embedded memory
    Patent number: 10276779
    Abstract: The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Tsung-Hsueh Yang
  • Method for legalizing mixed-cell height standard cells of IC
    Patent number: 10275559
    Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
  • TOP ELECTRODE CAP STRUCTURE FOR EMBEDDED MEMORY
    Publication number: 20190067559
    Abstract: The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Yao-Wen Chang, Tsung-Hsueh Yang
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20190067246
    Abstract: A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Guan-Wei Wu, Chu-Yung Liu, Yao-Wen Chang, I-Chen Yang
  • Semiconductor device having a multi-layer, metal-containing film
    Patent number: 10176999
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai
  • Structure and method to expose memory cells with different sizes
    Patent number: 10163651
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • SEMICONDUCTOR DEVICE, FILM STACK AND MANUFACTURING METHOD THEREOF
    Publication number: 20180337051
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Yao-Wen CHANG, Jian-Shiou HUANG, Cheng-Yuan TSAI
  • Semiconductor device and method of manufacturing the same
    Patent number: 10115896
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yao-Wen Chang, Cheng-Yuan Tsai, Chin-Wei Liang, Yen-Chang Chu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180301626
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: HAI-DANG TRINH, YAO-WEN CHANG, CHENG-YUAN TSAI, CHIN-WEI LIANG, YEN-CHANG CHU