Abstract: A regenerated cutting blade to be mounted and used in a shearing type grinder. The cutting blade includes a fixed part and a blade tip projecting outward from this fixed part, in which the blade tip has a leading edge pointed toward the rotating direction. Side edges 110 on the lateral side outer periphery including the blade tip, the leading end edge and the side edges are regenerated and formed by build-up welding. The lateral sides are provided with slip preventive build-up welding parts 111, 112, 113 extending from the side edges 110 toward the central side of its rotation or the central direction, and the build-up welding parts are formed by three regenerating processes.

Abstract: A regenerating method of a cutting blade to be repaired includes a chamfering step of chamfering a leading edge part and side edge parts of a cutting blade, a build-up welding step of welding a build-up on the chamfered leading edge part and the chamfered side edge parts, and a processing step of regenerating and processing build-up welding portions of the cutting blade into a specified shape of the leading edge part and the side edge parts, and of the build-up welding portions formed on the side edge parts, such that a dimension L1 of a lateral build-up weld zone is 1 to 3 times a dimension L2 of an outer build-up weld zone.

Abstract: To present a regenerated cutting blade, capable of regenerating efficiently by saving the cost and labor for regenerating a cutting blade, and improved in the grinding efficiency of a shearing type grinder to be close to that of a new cutting blade, when mounted and used in a shearing type grinder, including a fixed part 125, and a blade tip 127 projecting outward from this fixed part 125, in which the blade tip 127 has a leading end edge 109 pointed toward the rotating direction, and side edges 110 on the lateral side outer periphery including the blade tip 127, the leading end edge 109 and the side edges 110 are regenerated and formed by build-up welding, and the lateral sides are provided with slip preventive build-up welding parts 111, 112, 113 of the workpiece extending from the side edges 110 toward the central side of its rotation or the central direction, being formed by three regenerating processes.

Abstract: A regenerating method of a cutting blade to be repaired includes a chamfering step of chamfering the leading edge part and the side edge parts of a cutting blade, a build-up welding step of welding a build-up on the chamfered leading edge part and side edge parts, and a processing step of regenerating and processing build-up welding portions of the cutting blade into a specified shape of leading edge part and side edge parts, and of the side build-up welding portions formed on the side edge part, dimension L1 of a lateral build-up weld zone is 1 to 3 times of dimension L2 of an outer build-up weld zone.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, each of which is arranged at a position of between a word line and a bit line, a row decoder, and a bit line control circuit. And when data is to be read out from the memory cell, a charge control circuit controls the gate voltages of a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, so that the bit line is charged in accordance with a first characteristic obtained by increasing a current driving capacity of the first transistor during a desired period after start of charge of the bit line, and the bit line is then charged in accordance with a second characteristic obtained by returning the current driving capacity of the first transistor to the lower current driving capacity after elapse of the desired period.

Abstract: A method for controlling a threshold value in a nonvolatile semiconductor memory device, includes: performing writing at least once on at least one of the memory cells to be adjusted to a state other than an erased state with an applied voltage that does not cause excess writing, with verify reading being not performed; and performing verify reading by applying a verify voltage corresponding to a target threshold value of the memory cell after the writing is performed on the at least one of the memory cells to be adjusted to the state other than the erased state, and, when the threshold value of the memory cell is determined to be lower than the target threshold value, repeating the writing with the applied voltage that does not cause excess writing and the verify reading until the threshold value of the memory cell becomes equal to or higher than the target threshold value.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.

Abstract: A semiconductor storage apparatus has a control circuit. The control circuit deactivates the first and second amplifier circuits, turns off the first, second, fourth and fifth switch circuits, and turns on the third and sixth switch circuits in response to an external signal based on reduction of current dissipation of a power supply which supplies the power supply voltage.

Abstract: A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other.

Abstract: A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, each of which is arranged at a position of between a word line and a bit line, a row decoder, and a bit line control circuit. And when data is to be read out from the memory cell, a charge control circuit controls the gate voltages of a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, so that the bit line is charged in accordance with a first characteristic obtained by increasing a current driving capacity of the first transistor during a desired period after start of charge of the bit line, and the bit line is then charged in accordance with a second characteristic obtained by returning the current driving capacity of the first transistor to the lower current driving capacity after elapse of the desired period.

Abstract: A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell.

Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: Provided is a magnesium-silicon composite material which contains Mg2Si as an intermetallic compound imposing no burden on the environment, is suitable for use as a material for thermoelectric conversion modules, and has excellent thermoelectric conversion performance. The magnesium-silicon composite material has a dimensionless figure-of-merit parameter at 866K of 0.665 or larger. This magnesium-silicon composite material can have high thermoelectric conversion performance when used in, for example, a thermoelectric conversion module.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.

Abstract: A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.